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CLC number: TN91

On-line Access: 2016-03-07

Received: 2015-03-15

Revision Accepted: 2015-09-08

Crosschecked: 2016-02-23

Cited: 18

Clicked: 3614

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Debashis De

http://orcid.org/0000-0002-9688-9806

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Frontiers of Information Technology & Electronic Engineering  2016 Vol.17 No.3 P.224-236

http://doi.org/10.1631/FITEE.1500079


Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication


Author(s):  Jadav Chandra Das, Debashis De

Affiliation(s):  Department of Computer Science and Engineering, West Bengal University of Technology, Kolkata 700064, India; more

Corresponding email(s):   jadav2u@gmail.com, dr.debashis.de@gmail.com

Key Words:  Quantum-dot cellular automata (QCA), Parity generator, Parity checker, Feynman gate, Nanocommunication, Power dissipation


Jadav Chandra Das, Debashis De. Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(3): 224-236.

@article{title="Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication",
author="Jadav Chandra Das, Debashis De",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="17",
number="3",
pages="224-236",
year="2016",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1500079"
}

%0 Journal Article
%T Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication
%A Jadav Chandra Das
%A Debashis De
%J Frontiers of Information Technology & Electronic Engineering
%V 17
%N 3
%P 224-236
%@ 2095-9184
%D 2016
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1500079

TY - JOUR
T1 - Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication
A1 - Jadav Chandra Das
A1 - Debashis De
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 17
IS - 3
SP - 224
EP - 236
%@ 2095-9184
Y1 - 2016
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.1500079


Abstract: 
quantum-dot cellular automata (QCA) is an emerging area of research in reversible computing. It can be used to design nanoscale circuits. In nanocommunication, the detection and correction of errors in a received message is a major factor. Besides, device density and power dissipation are the key issues in the nanocommunication architecture. For the first time, QCA-based designs of the reversible low-power odd parity generator and odd parity checker using the feynman gate have been achieved in this study. Using the proposed parity generator and parity checker circuit, a nanocommunication architecture is proposed. The detection of errors in the received message during transmission is also explored. The proposed QCA feynman gate outshines the existing ones in terms of area, cell count, and delay. The quantum costs of the proposed conventional reversible circuits and their QCA layouts are calculated and compared, which establishes that the proposed QCA circuits have very low quantum cost compared to conventional designs. The energy dissipation by the layouts is estimated, which ensures the possibility of QCA nano-device serving as an alternative platform for the implementation of reversible circuits. The stability of the proposed circuits under thermal randomness is analyzed, showing the operational efficiency of the circuits. The simulation results of the proposed design are tested with theoretical values, showing the accuracy of the circuits. The proposed circuits can be used to design more complex low-power nanoscale lossless nanocommunication architecture such as nano-transmitters and nano-receivers.

This paper illustrates the design of reversible odd parity generator and odd parity checker using proposed QCA Feynman gate. Then an error detection scheme in Nanocommunication is achieved. The technical depth of the manuscript is appropriate.

基于量子原胞自动机的纳米通信可逆低功耗奇偶生成器与奇偶校验器设计

目的:量子原胞自动机(QCA)是可逆计算领域的新兴方向。QCA可用于设计纳米级别的电路。在纳米通信领域,接收信号差错检测及校正是一个重要环节。同时,器件密度和功率耗散是纳米通信系统的关键问题。本文利用QCA的低器件密度和超低功耗特性,助力低功耗微纳级别可逆奇偶发生与校验器的设计。
创新点:基于QCA,第一次实现了使用费曼门的可逆低功耗奇偶生成器和奇偶校验器设计。
方法:基于本文提出的奇偶生成器和奇偶校验器电路,设计了一种纳米通信系统,并研究了传输中接收信号的差错检测。1.在QCA中设计可逆费曼门;2.在等量子成本的基础上,使用费曼门实现可逆奇偶生成与可逆奇偶校验电路;3.在相同量子成本和无用值的基础上,使用可逆奇偶生成器与校验器设计纳米通信系统;4.首次在QCA中实现可逆奇偶生成器、奇偶校验器与纳米通信电路;5.对可逆电路及其QCA布局进行量子成本分析;6.在面积、延迟和胞元计数等方面比对所述QCA费曼门与现有费曼门电路;7.估算所述设计的能量耗散;8.使用热随机性,观察输出胞元的极性,测量电路的可靠性。
结论:本文所提出的QCA费曼门在面积、原胞计数和延迟方面,超过了现有费曼门的指标水平。通过计算、比对传统可逆电路及其相应的QCA布局,证明QCA电路具有极低的量子成本。通过估计QCA电路的功率耗散,证明QCA微纳器件是可逆电路的可行平台。通过在热随机性下分析QCA电路的可靠性,证明所述电路的工作有效性。通过比对仿真结果与理论值,证明所述电路的精度。所述电路可以用于设计更为复杂的低功率微纳无损耗纳米通信系统(例如微纳发射器和微纳接收器)。

关键词:量子原胞自动机(QCA);奇偶生成器;奇偶校验器;费曼门;纳米通信;功率耗散

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