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CLC number: TN91

On-line Access: 2016-03-07

Received: 2015-03-15

Revision Accepted: 2015-09-08

Crosschecked: 2016-02-23

Cited: 18

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Citations:  Bibtex RefMan EndNote GB/T7714


Debashis De


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Frontiers of Information Technology & Electronic Engineering  2016 Vol.17 No.3 P.224-236


Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication

Author(s):  Jadav Chandra Das, Debashis De

Affiliation(s):  Department of Computer Science and Engineering, West Bengal University of Technology, Kolkata 700064, India; more

Corresponding email(s):   jadav2u@gmail.com, dr.debashis.de@gmail.com

Key Words:  Quantum-dot cellular automata (QCA), Parity generator, Parity checker, Feynman gate, Nanocommunication, Power dissipation

Jadav Chandra Das, Debashis De. Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(3): 224-236.

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A1 - Jadav Chandra Das
A1 - Debashis De
J0 - Frontiers of Information Technology & Electronic Engineering
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quantum-dot cellular automata (QCA) is an emerging area of research in reversible computing. It can be used to design nanoscale circuits. In nanocommunication, the detection and correction of errors in a received message is a major factor. Besides, device density and power dissipation are the key issues in the nanocommunication architecture. For the first time, QCA-based designs of the reversible low-power odd parity generator and odd parity checker using the feynman gate have been achieved in this study. Using the proposed parity generator and parity checker circuit, a nanocommunication architecture is proposed. The detection of errors in the received message during transmission is also explored. The proposed QCA feynman gate outshines the existing ones in terms of area, cell count, and delay. The quantum costs of the proposed conventional reversible circuits and their QCA layouts are calculated and compared, which establishes that the proposed QCA circuits have very low quantum cost compared to conventional designs. The energy dissipation by the layouts is estimated, which ensures the possibility of QCA nano-device serving as an alternative platform for the implementation of reversible circuits. The stability of the proposed circuits under thermal randomness is analyzed, showing the operational efficiency of the circuits. The simulation results of the proposed design are tested with theoretical values, showing the accuracy of the circuits. The proposed circuits can be used to design more complex low-power nanoscale lossless nanocommunication architecture such as nano-transmitters and nano-receivers.

This paper illustrates the design of reversible odd parity generator and odd parity checker using proposed QCA Feynman gate. Then an error detection scheme in Nanocommunication is achieved. The technical depth of the manuscript is appropriate.




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[1]Aghababa, H., Forouzandeh, B., Afzali-Kusha, A., 2012. High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility. J. Zhejiang Univ.-Sci. C (Comput. & Electron.), 13(6):460-471.

[2]Agrawal, P., Ghosh, B., 2015. Innovative design methodologies in quantum-dot cellular automata. Int. J. Circ. Theory Appl., 43(2):253-262.

[3]Akter, R., Islam, N., Waheed, S., 2015. Implementation of reversible logic gate in quantum dot cellular automata. Int. J. Comput. Appl., 109(1):41-44.

[4]Biswas, P., Gupta, N., Patidar, N., 2014. Basic reversible logic gates and its QCA implementation. Int. J. Eng. Res. Appl., 4(6):12-16.

[5]Das, J.C., De, D., 2012. Quantum Dot-Cellular Automata based cipher text design for nano-communication. Int. Conf. on Radar, Communication and Computing, p.224-229.

[6]Das, J.C., De, D., 2015a. Reversible binary to grey and grey to binary code converter using QCA. IETE J. Res., 61(3): 223-229.

[7]Das, J.C., De, D., 2015b. Reversible comparator design using quantum dot-cellular automata. IETE J. Res., in press.

[8]Das, J.C., Debnath, B., De, D., 2015. Image steganography using quantum dot cellular automata. Quant. Matter, 4(5):504-517.

[9]Das, K., De, D., 2010. Characterization, test and logic synthesis of novel conservative & reversible logic gates for QCA. Int. J. Nanosci., 9(3):201-214.

[10]Das, K., De, D., 2011. Characterization, applicability and defect analysis for tiles nanostructure of quantum dot cellular automata. Mol. Simul., 37(3):210-225.

[11]Das, K., De, D., De, M., 2013. Realisation of semiconductor ternary quantum dot cellular automata. IET Micro Nano Lett., 8(5):258-263.

[12]Hung, W.N.N., Song, X., Yang, G., et al., 2006. Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst., 25(9): 1652-1663.

[13]ITRS (International Technology Roadmap for Semiconductors), 2005. Available from http://www.itrs.net.

[14]Kunalan, D., Cheong, C.L., Chau, C.F., et al., 2014. Design of a 4-bit adder using reversible logic in quantum-dot cellular automata (QCA). IEEE Int. Conf. on Semiconductor Electronics, p.60-63.

[15]Lent, C., Tougaw, P., 1997. A device architecture for computing with quantum dots. Proc. IEEE, 85(4):541-557.

[16]Liu, W., Srivastava, S., Lu, L., et al., 2012. Are QCA cryptographic circuits resistant to power analysis attack IEEE Trans. Nanotechnol., 11(6):1239-1251.

[17]Ma, X., 2008. Physical/Biochemical Inspired Computing Models for Reliable Nano-Technology Systems. PhD Thesis, Northeastern University, Boston, Massachusetts, United States.

[18]Mano, M.M., Ciletti, M.D., 2011. Digital Design with an Introduction to Verilog HDL (5th Ed.). Pearson Education, India.

[19]Mardiris, V.A., Karafyllidis, I.G., 2010. Design and simulation of modular 2n to 1 quantum-dot cellular automata (QCA) multiplexers. Int. J. Circ. Theory Appl., 38(8):771-785.

[20]Mohammadi, Z., Mohammadi, M., 2014. Implementing a one-bit reversible full adder using quantum-dot cellular automata. Quant. Inform. Process., 13(9):2127-2147.

[21]Orlov, A.O., Amlani, I., Bernstein, G.H., et al., 1997. Realization of a functional cell for quantum-dot cellular automata. Science, 277(5328):928-930.

[22]Pudi, V., Sridharan, K., 2011. Efficient design of a hybrid adder in quantum-dot cellular automata. IEEE Trans. VLSI Syst., 19(9):1535-1548.

[23]Rahman, M.A., Khatun, F., Sarkar, A., et al., 2013. Design and implementation of Feynman gate in quantum-dot cellular automata (QCA). Int. J. Comput. Sci. Iss., 10(4):167-170.

[24]Shabeena, S., Pathak, J., 2015. Design and verification of reversible logic gates using quantum dot cellular automata. Int. J. Comput. Appl., 114(4):39-42.

[25]Sheikhfaal, S., Angizi, S., Sarmadi, S., et al., 2015. Designing efficient QCA logical circuits with power dissipation analysis. Microelectron. J., 46(6):462-471.

[26]Silva, D.S., Sardinha, L.H.B., Vieira, M.A.M., et al., 2015. Robust serial nanocommunication with QCA. IEEE Trans. Nanotechnol., 14(3):464-472.

[27]Smolin, J.A., DiVincenzo, D.P., 1996. Five two-bit quantum gates are sufficient to implement the quantum Fredkin gate. Phys. Rev. A, 53(4):2855-2856.

[28]Srivastava, S., Asthana, A., Bhanja, S., et al., 2011. QCAPro— an error power estimation tool for QCA circuit design. Proc. IEEE Int. Symp. on Circuits and Systems, p.2377-2380.

[29]Toffoli, T., 1980. Reversible Computing. Tech Memo MIT/LCS/TM-151, MIT Lab for Computer Science.

[30]Walus, K., Dysart, T.J., Jullien, G.A., et al., 2004. QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata. IEEE Trans. Nanotechnol., 3(1):26-31.

[31]Xiao, L.R., Chen, X.X., Ying, S.Y., 2012. Design of dual-edge triggered flip-flops based on quantum-dot cellular automata. J. Zhejiang Univ.-Sci. C (Comput. & Electron.), 13(5):385-392.

[32]Yang, X., Cai, L., Huang, H., et al., 2012. A comparative analysis and design of quantum-dot cellular automata memory cell architecture. Int. J. Circ. Theory Appl., 40(1):93-103.

[33]Zhang, R., Walus, K., Wang, W., et al., 2004. A method of majority logic reduction for quantum cellular automata. IEEE Trans. Nanotechnol., 3(4):443-450.

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