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CLC number: TN303

On-line Access: 2015-12-07

Received: 2015-04-07

Revision Accepted: 2015-06-25

Crosschecked: 2015-11-06

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Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Xiao Chen

http://orcid.org/0000-0002-8943-8679

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Frontiers of Information Technology & Electronic Engineering  2015 Vol.16 No.12 P.1088-1098

http://doi.org/10.1631/FITEE.1500111


A driving pulse edge modulation technique and its complex programming logic devices implementation


Author(s):  Xiao Chen, Dong-chang Qu, Yong Guo, Guo-zhu Chen

Affiliation(s):  1Electrical Engineering Department, Zhejiang University, Hangzhou 310027, China; more

Corresponding email(s):   andrer007@163.com, qudongchang3939@163.com, rinatoon@163.com, gzchen@zju.edu.cn

Key Words:  Driving pulse edge modulation, Switching voltage spike, Complex programmable logic device (CPLD), Active gate drive


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Xiao Chen, Dong-chang Qu, Yong Guo, Guo-zhu Chen. A driving pulse edge modulation technique and its complex programming logic devices implementation[J]. Frontiers of Information Technology & Electronic Engineering, 2015, 16(12): 1088-1098.

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Abstract: 
With the continual increase in switching speed and rating of power semiconductors, the switching voltage spike becomes a serious problem. This paper describes a new technique of driving pulse edge modulation for insulated gate bipolar transistors (IGBTs). By modulating the density and width of the pulse trains, without regulating the hardware circuit, the slope of the gate driving voltage is controlled to change the switching speed. This technique is used in the driving circuit based on complex programmable logic devices (CPLDs), and the switching voltage spike of IGBTs can be restrained through software, which is easier and more flexible to adjust. Experimental results demonstrate the effectiveness and practicability of the proposed method.

This paper is well written and interesting. A new digital driving control method is proposed by the authors to control the switching speed and its associated voltage spike issue.

驱动脉冲边沿调制技术及其CPLD实现

目的:针对随功率半导体器件开关速度和功率等级的不断提高而产生的严峻的开关电压尖峰问题,以IGBT为对象,提出一种驱动脉冲边沿调制技术,实现对门极驱动电压边沿斜率的调节,抑制IGBT的电压尖峰。
创新点:利用面积等效原理,将门极驱动脉冲信号的边沿映射成一簇脉冲序列,门极驱动电压的上升或下降段即为这些脉冲信号响应的叠加。通过调节脉冲序列的密度和脉冲宽度,调节门极驱动电压边沿斜率,从而调节开关速度限制开关电压尖峰。
方法:将传统的门极驱动信号的边沿映射成一簇脉冲序列,将PWM信号转换为MPWM信号,则脉冲边沿的调制也即为调制该脉冲序列的密度和脉冲宽度,有双向脉冲序列调制BPTM和单向脉冲序列调制UPTM两种方法。对于BPTM调试,MPWM信号为正表示正的驱动电压vge,on被接入,MPWM信号为负则表示负的驱动电压vge,off被接入。在IGBT开通时期,若驱动电路的响应能力有限,这种调试方法下门极驱动电压的边沿呈现明显锯齿状,使得门极电压在IGBT导通阈值电压vge,th附近波动,引起IGBT的伪导通,故而可改进为UPTM方法。对于UPTM调制,当调试上升沿时,高电平信号表示接入正的驱动电压vge,on,低电平信号表示不接入驱动电压从而保持门极电压为当前值;当调试下降沿时,高电平信号表示接入负的驱动电压vge,off,低电平信号表示不接入驱动电压从而保持门极电压为当前值。文中图9是采用CPLD的具体驱动电路,在BPTM模式下,MOSFET1管和MOSFET2管交替开通和关断,以调制驱动脉冲边沿;在UPTM模式下,只有一个MOSFET管开通和关断来调制驱动脉冲边沿,而另一个MOSFET管被封锁。
结论:采用驱动脉冲边沿调制技术(双向脉冲序列调制BPTM和单向脉冲序列调制UPTM),可以明显抑制开关尖峰。由于基于数字技术,且只需要一个数字芯片,不需要改变硬件电路结构,可通过软件来实现对驱动脉冲边沿的调控,使其适用于不同工况,具有较强的通用性和灵活性。其中,采用单向脉冲序列调制(UPTM)可以解决IGBT伪导通问题,该调制技术对驱动电路响应速度要求不高的特点使其更便于应用。

关键词:驱动脉冲边沿调制;开关电压尖峰;复杂可编程逻辑器件(CPLD);有源门极驱动

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