Full Text:   <868>

Summary:  <299>

CLC number: TN432

On-line Access: 2016-03-07

Received: 2015-07-06

Revision Accepted: 2015-11-18

Crosschecked: 2016-02-20

Cited: 1

Clicked: 1456

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Li-rong Zheng

http://orcid.org/0000-0001-9588-0239

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Frontiers of Information Technology & Electronic Engineering  2016 Vol.17 No.3 P.258-264

10.1631/FITEE.1500210


Design and simulation of a standing wave oscillator based PLL


Author(s):  Wei Zhang, You-de Hu, Li-rong Zheng

Affiliation(s):  State Key Lab of ASIC & System, Fudan University, Shanghai 200433, China; more

Corresponding email(s):   wei_zhang@fudan.edu.cn, lirong@kth.se

Key Words:  Standing wave oscillator (SWO), Clock distribution, Phase locked loop (PLL), Varactor


Wei Zhang, You-de Hu, Li-rong Zheng. Design and simulation of a standing wave oscillator based PLL[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(3): 258-264.

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Abstract: 
A standing wave oscillator (SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor (IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop (PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P complementary metal-oxide-semiconductor (CMOS) technology, and can be used directly in a high performance multi-core microprocessor.

This paper shows an interesting and meaningful design of a standing wave oscillator based PLL, which has a potential for future PLL application to reduced clock power and clock skew.

基于驻波振荡器的PLL设计与仿真

目的:基于标准CMOS工艺实现频率可调节驻波振荡器结构,研究该结构在高性能微处理器中的应用方式并实现基于该结构的PLL设计。
创新点:分析了反型MOS管可变电容在驻波振荡器中不同分布方式对频率调节范围和功耗的影响,根据分析结果设计了基于频率可调节驻波振荡器的PLL。该PLL不仅实现了50%的时钟调节范围,而且可以作为时钟分布网络直接应用于多核处理器结构中。
方法:首先分析了不同阈值对反型MOS管可变电容的影响(图3),提出了基于该可变电容结构的两类驻波振荡器频率调节方式(图4),通过仿真对比分析了两者频率调节和功耗的差异(图5、6)。然后基于分析结果设计了基于频率可调节驻波振荡器的PLL(图7),分析了该PLL的频率锁定过程(图9)。最后分析了该PLL在高性能微处理器设计中的应用方式(图11)。
结论:采用反型MOS管可变电容可实现频率可调节驻波振荡器结构,基于该驻波振荡器可以设计频率调节范围达到50%的PLL,满足高性能微处理器对时钟的要求。

关键词:驻波振荡器;时钟分布;可变电容;变抗器

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

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[9]O’Mahony, F., Yue, C.P., Horowitz, M.A., et al., 2003. A 10-GHz global clock distribution using coupled standing-wave oscillators. IEEE J. Sol.-State Circ., 38(11):1813-1820.

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