Full Text:   <1968>

Summary:  <265>

CLC number: TN79

On-line Access: 2016-10-08

Received: 2015-07-07

Revision Accepted: 2015-09-24

Crosschecked: 2016-09-20

Cited: 3

Clicked: 2460

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Mohammad Hossein Moaiyeri

http://orcid.org/0000- 0001-9711-7923

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Frontiers of Information Technology & Electronic Engineering  2016 Vol.17 No.10 P.1056-1066

http://doi.org/10.1631/FITEE.1500214


Design and analysis of carbon nanotube FET based quaternary full adders


Author(s):  Mohammad Hossein Moaiyeri, Shima Sedighiani, Fazel Sharifi, Keivan Navi

Affiliation(s):  Faculty of Electrical Engineering, Shahid Beheshti University, Tehran 1983963113, Iran; more

Corresponding email(s):   h_moaiyeri@sbu.ac.ir

Key Words:  Nanoelectronics, Carbon nanotube FET, Multiple-valued logic, Quaternary logic


Mohammad Hossein Moaiyeri, Shima Sedighiani, Fazel Sharifi, Keivan Navi. Design and analysis of carbon nanotube FET based quaternary full adders[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(10): 1056-1066.

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publisher="Zhejiang University Press & Springer",
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Abstract: 
CMOS binary logic is limited by short channel effects, power density, and interconnection restrictions. The effective solution is non-silicon multiple-valued logic (MVL) computing. This study presents two high-performance quaternary full adder cells based on carbon nanotube field effect transistors (CNTFETs). The proposed designs use the unique properties of CNTFETs such as achieving a desired threshold voltage by adjusting the carbon nanotube diameters and having the same mobility as p-type and n-type devices. The proposed circuits were simulated under various test conditions using the Synopsys HSPICE simulator with the 32 nm Stanford comprehensive CNTFET model. The proposed designs have on average 32% lower delay, 68% average power, 83% energy consumption, and 77% static power compared to current state-of-the-art quaternary full adders. Simulation results indicated that the proposed designs are robust against process, voltage, and temperature variations, and are noise tolerant.

In this paper two CNTFET based quaternary full adder cells design is proposed. The proposed design uses the unique properties of CNTFETs such as having desired threshold voltage by adjusting the CNT diameters and having same mobility of p-type and n-type devices. The proposed circuits are simulated under various test conditions using Synopsys HSPICE simulator with 32 nm Stanford comprehensive CNTFET model.

碳纳米管场效应管四进制全加器设计与分析

概要:CMOS二进制逻辑受短沟道效应、功率密度及互连约束等条件的限制。非硅多值逻辑计算是克服上述问题的一种有效方案。本研究在碳纳米管场效应管(carbon nanotube field effect transistors, CNTFET)的基础上提出了两种高性能四进制全加单元。该全加单元利用了CNTFET独有的特性,如目标电压阈值可通过调整碳纳米管管径控制、CNTFET具有与p型和n型器件相同的迁移性。通过在Synopsys HSPICE中使用32 nm斯坦福综合CNTFET模型,在多种测试条件下对所述电路单元进行了仿真。与当前水平的四进制全加器相比,本文所采用的设计平均降低延迟32%,所需平均功率、能耗及静态功率分别为现有水平的68%、83%及77%。仿真结果表明,所述设计在生产制程、电压、温度变化、噪声耐受方面具有较好的鲁棒性。

关键词:纳米电子;碳纳米管场效应管;多值逻辑;四进制逻辑

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

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Open peer comments: Debate/Discuss/Question/Opinion

<1>

Anna Gina Perri@Department of Electrical and Information Engineering, Polytechnic University of Bari, ITALY<annagina.perri@poliba.it>

2016-12-12 18:49:50

Two new CNTFET based quaternary full adder cells are proposed. According to properties of CNTFETs, the design of MVL circuits is easier and efficient compared to using MOSFETs.
The circuits are examined using a HSPICE simulator with a 32 nm CNTFET model.
The simulation results, conducted under various conditions, indicate that the proposed circuits are faster, consume less power, and consequently have a lower energy consumption than the state-of-the-art quaternary full adders.
The paper is well-written and well-organized and clearly delivers the message to the reader. In particular:
1. There are no technical errors and/or inconsistencies.
2. The Statements are clear, as well as the Conclusions.
3. The level of English is good, Figures are adequate and References are current.
According to my opinion, this paper does not need any review and it may be published.
My only suggestion is to add in References the following two papers:

R. Marani, A.G. Perri: “A Comparison of CNTFET Models through the Design of a SRAM Cell”, ECS Journal of Solid State Science and Technology, vol. 5(10), 2016, pp. M118-M126, doi:10.1149/2.0161610jss.

R. Marani, A.G. Perri: “A Simulation Study of Analogue and Logic Circuits with CNTFETs”, ECS Journal of Solid State Science and Technology, vol. 5(6), 2016, pp. M38-M43, doi:10.1149/2.0121605jss.

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