Full Text:   <1083>

Summary:  <172>

CLC number: TP316

On-line Access: 2018-04-09

Received: 2016-08-16

Revision Accepted: 2016-11-07

Crosschecked: 2018-02-15

Cited: 0

Clicked: 2058

Citations:  Bibtex RefMan EndNote GB/T7714


Kai Lu


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Frontiers of Information Technology & Electronic Engineering  2018 Vol.19 No.2 P.192-205


Versionized process based on non-volatile random-access memory for fine-grained fault tolerance

Author(s):  Wen-zhe Zhang, Kai Lu, Xiao-ping Wang

Affiliation(s):  Science and Technology on Parallel and Distributed Processing Laboratory, College of Computer, National University of Defense Technology, Changsha 410073, China

Corresponding email(s):   lukainudt@163.com

Key Words:  Non-volatile memory, Byte-persistence, Versionized process, Version number

Wen-zhe Zhang, Kai Lu, Xiao-ping Wang. Versionized process based on non-volatile random-access memory for fine-grained fault tolerance[J]. Frontiers of Information Technology & Electronic Engineering, 2018, 19(2): 192-205.

@article{title="Versionized process based on non-volatile random-access memory for fine-grained fault tolerance",
author="Wen-zhe Zhang, Kai Lu, Xiao-ping Wang",
journal="Frontiers of Information Technology & Electronic Engineering",
publisher="Zhejiang University Press & Springer",

%0 Journal Article
%T Versionized process based on non-volatile random-access memory for fine-grained fault tolerance
%A Wen-zhe Zhang
%A Kai Lu
%A Xiao-ping Wang
%J Frontiers of Information Technology & Electronic Engineering
%V 19
%N 2
%P 192-205
%@ 2095-9184
%D 2018
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1601477

T1 - Versionized process based on non-volatile random-access memory for fine-grained fault tolerance
A1 - Wen-zhe Zhang
A1 - Kai Lu
A1 - Xiao-ping Wang
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 19
IS - 2
SP - 192
EP - 205
%@ 2095-9184
Y1 - 2018
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.1601477

Non-volatile random-access memory (NVRAM) technology is maturing rapidly and its byte-persistence feature allows the design of new and efficient fault tolerance mechanisms. In this paper we propose the versionized process (VerP), a new process model based on NVRAM that is natively non-volatile and fault tolerant. We introduce an intermediate software layer that allows us to run a process directly on NVRAM and to put all the process states into NVRAM, and then propose a mechanism to versionize all the process data. Each piece of the process data is given a special version number, which increases with the modification of that piece of data. The version number can effectively help us trace the modification of any data and recover it to a consistent state after a system crash. Compared with traditional checkpoint methods, our work can achieve fine-grained fault tolerance at very little cost.


概要:新型非易失存储器(NVRAM)提供的字节粒度持久且非易失新特性,将有力支持新型容错技术的设计。提出一个基于NVRAM的新型容错进程模型--版本化进程(versionized process,VerP)。该进程模型通过在传统软硬件之间引入一个软件中间层,将软硬件解耦合,在NVRAM上重新组织进程所有数据,从而支持进程在NVRAM的天然容错。进一步,赋予进程中每个数据一个版本号,通过更新版本号实现进程非易失数据的一致性更新。与传统检查点机制相比,VerP可高效支持细粒度容错。


Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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