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Journal of Zhejiang University SCIENCE C 1998 Vol.-1 No.-1 P.

http://doi.org/10.1631/FITEE.1900653


A 0.2-2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP


Author(s):  Wei ZOU, Da-ming REN, Xue-cheng ZOU

Affiliation(s):  the School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China

Corresponding email(s):   weizou@hust.edu.cn, damingren@hust.edu.cn, estxczou@hust.edu.cn

Key Words:  Frequency synthesizer, Charge pump (CP), Voltage-controlled oscillator (VCO), Current mismatch, Phase noise


Wei ZOU, Da-ming REN, Xue-cheng ZOU. A 0.2-2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP[J]. Frontiers of Information Technology & Electronic Engineering, 1998, -1(-1): .

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Abstract: 
A 0.2-2.43 GHz fractional-N frequency synthesizer is presented for multi-standard wireless communication systems, in which the scheme adopts low phase noise voltage-controlled oscillators (VCOs) and a charge pump (CP) with reduced current mismatch. The VCOs that determine the out-band phase noise of a phase-locked loop (PLL)-based frequency synthesizer are optimized using an automatic amplitude control technique and a high-quality factor figure-8-shaped inductor. A CP with a mismatch suppression architecture is proposed and utilized to improve the CP current matching and reduce the PLL phase errors. Theoretical analyses are also presented to investigate the influence of the current mismatch on the output performance of PLLs. Fabricated in a TSMC 0.18-µm CMOS process, the prototype operates from 0.2 to 2.43 GHz. The PLL synthesizer achieves an in-band phase noise of −96.8 dBc/Hz and an out-band phase noise of −122.8 dBc/Hz at 2.43 GHz carrier. The RMS jitter is 1.2 ps under the worst case and the measured reference spurs are better than −65.3 dBc. The current consumption is 15.2 mA and the die occupies 850µm×920µm.

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