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CLC number: TP333

On-line Access: 2022-07-21

Received: 2021-05-26

Revision Accepted: 2022-07-21

Crosschecked: 2021-10-07

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Citations:  Bibtex RefMan EndNote GB/T7714




Biplab Kumar SIKDAR


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Frontiers of Information Technology & Electronic Engineering  2022 Vol.23 No.7 P.1110-1126


Cellular automata based multi-bit stuck-at fault diagnosis for resistive memory

Author(s):  Sutapa SARKAR, Biplab Kumar SIKDAR, Mousumi SAHA

Affiliation(s):  Department of Electronics and Communication Engineering, Seacom Engineering College, Howrah, West Bengal 711302, India; more

Corresponding email(s):   sutapa321@gmail.com, biplab@cs.iiests.ac.in, msaha.nitd@gmail.com

Key Words:  Resistive memory, Cell reliability, Stuck-at fault diagnosis, Single-length-cycle single-attractor cellular automata, Single-length-cycle two-attractor cellular automata, Single-length-cycle multiple-attractor cellular automata

Sutapa SARKAR, Biplab Kumar SIKDAR, Mousumi SAHA. Cellular automata based multi-bit stuck-at fault diagnosis for resistive memory[J]. Frontiers of Information Technology & Electronic Engineering, 2022, 23(7): 1110-1126.

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This paper presents a group-based dynamic stuck-at fault diagnosis scheme intended for resistive random-access memory (ReRAM). Traditional static random-access memory, dynamic random-access memory, NAND, and NOR flash memory are limited by their scalability, power, package density, and so forth. Next-generation memory types like ReRAMs are considered to have various advantages such as high package density, non-volatility, scalability, and low power consumption, but cell reliability has been a problem. Unreliable memory operation is caused by permanent stuck-at faults due to extensive use of write- or memory-intensive workloads. An increased number of stuck-at faults also prematurely limit chip lifetime. Therefore, a cellular automaton (CA) based dynamic stuck-at fault-tolerant design is proposed here to combat unreliable cell functioning and variable cell lifetime issues. A scalable, block-level fault diagnosis and recovery scheme is introduced to ensure readable data despite multi-bit stuck-at faults. The scheme is a novel approach because its goal is to remove all the restrictions on the number and nature of stuck-at faults in general fault conditions. The proposed scheme is based on Wolfram's null boundary and periodic boundary CA theory. Various special classes of CAs are introduced for 100% fault tolerance: single-length-cycle single-attractor cellular automata (SACAs), single-length-cycle two-attractor cellular automata (TACAs), and single-length-cycle multiple-attractor cellular automata (MACAs). The target micro-architectural unit is designed with optimal space overhead.


Sutapa SARKAR1, Biplab Kumar SIKDAR2, Mousumi SAHA3


Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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