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Received: 2002-08-06

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Journal of Zhejiang University SCIENCE A 2003 Vol.4 No.5 P.526~531

http://doi.org/10.1631/jzus.2003.0526


DPLL implementation in carrier acquisition and tracking for burst DS-CDMA receivers


Author(s):  GUAN Yun-feng, ZHANG Zhao-yang, Lai Li-feng

Affiliation(s):  Institute of Information and Communication Engineering, Zhejiang University, Hangzhou 310027, China; more

Corresponding email(s):   yfguan69@yahoo.com

Key Words:  CDMA, Digital phase locked loop(DPLL), Carrier frequency offset


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GUAN Yun-feng, ZHANG Zhao-yang, Lai Li-feng. DPLL implementation in carrier acquisition and tracking for burst DS-CDMA receivers[J]. Journal of Zhejiang University Science A, 2003, 4(5): 526~531.

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DOI - 10.1631/jzus.2003.0526


Abstract: 
This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challenging problem in CDMA system. According to different applications, different DPLL forms should be adopted to correct different maximum carrier offset in CDMA systems. One classical DPLL and two novel DPLL forms are discussed in the paper. The acquisition range of carrier offset can be widened by using the two novel DPLL forms without any performance degradation such as longer acquisition time or larger variance of the phase error. The maximum acquisition range is 1/(4T), where T is the symbol period. The design can be implemented by FPGA directly.

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Reference

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[6]Huang, W., Andonovic, I. and Nakagawa, M., 1998. PLL performance of DS-CDMA systems in the presence of phase noise, multiuser interference, and adding gaussian noise. IEEE Transactions on Communications, 46(11): 1507-1515.

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[8]Nezami, M.K., 2001. DSP-based carrier acquisition and tracking for burst TDMA mobile land and satellite receivers. Applied Microwave & Wireless, 13(9): 24-41.

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