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Journal of Zhejiang University SCIENCE A 2006 Vol.7 No.2 P.269~274

http://doi.org/10.1631/jzus.2006.A0269


Optimizing pipeline for a RISC processor with multimedia extension ISA


Author(s):  Xiao Zhi-bin, Liu Peng, Yao Ying-biao, Yao Qing-dong

Affiliation(s):  Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   xzb@zju.edu.cn, liupeng@isee.zju.edu.cn

Key Words:  Pipeline, RISC, Single-instruction-multiple-data (SIMD), Instruction set architecture (ISA), Multimedia extension


Xiao Zhi-bin, Liu Peng, Yao Ying-biao, Yao Qing-dong. Optimizing pipeline for a RISC processor with multimedia extension ISA[J]. Journal of Zhejiang University Science A, 2006, 7(2): 269~274.

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author="Xiao Zhi-bin, Liu Peng, Yao Ying-biao, Yao Qing-dong",
journal="Journal of Zhejiang University Science A",
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number="2",
pages="269~274",
year="2006",
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doi="10.1631/jzus.2006.A0269"
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%T Optimizing pipeline for a RISC processor with multimedia extension ISA
%A Xiao Zhi-bin
%A Liu Peng
%A Yao Ying-biao
%A Yao Qing-dong
%J Journal of Zhejiang University SCIENCE A
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%P 269~274
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%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.2006.A0269

TY - JOUR
T1 - Optimizing pipeline for a RISC processor with multimedia extension ISA
A1 - Xiao Zhi-bin
A1 - Liu Peng
A1 - Yao Ying-biao
A1 - Yao Qing-dong
J0 - Journal of Zhejiang University Science A
VL - 7
IS - 2
SP - 269
EP - 274
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.2006.A0269


Abstract: 
The 32-bit extensible embedded processor RISC3200 originating from an RTL prototype core is intended for low-cost consumer multimedia products. In order to incorporate the reduced instruction set and the multimedia extension instruction set in a unifying pipeline, a scalable super-pipeline technique is adopted. Several other optimization techniques are proposed to boost the frequency and reduce the average CPI of the unifying pipeline. Based on a data flow graph (DFG) with delay information, the critical path of the pipeline stage can be located and shortened. This paper presents a distributed data bypass unit and a centralized pipeline control scheme for achieving lower CPI. Synthesis and simulation showed that the optimization techniques enable RISC3200 to operate at 200 MHz with an average CPI of 1.16. The core was integrated into a media SOC chip taped out in SMIC 0.18-micron technology. Preliminary testing result showed that the processor works well as we expected.

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Reference

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[9] Liu, P., Wang, W.D., Xiao, Z.B., Lai, L.Y., Teng, Z.W., Yu, G.J., Yao, Y.B., Chen, K.M., Jiang, Z.D., Zhang, Y.X., Zhou, J., Cai, W.G., Zhai, Z.B., Shi, C., Yao, Q.D., 2005. MediaSOC: A System-on-Chip Architecture for Multimedia Application. IEEE International Workshop on VLSI Design and Video Technology (IWVDVT2005), Suzhou, China, p.161-164.

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