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Received: 2007-03-09

Revision Accepted: 2007-04-27

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Journal of Zhejiang University SCIENCE A 2007 Vol.8 No.10 P.1553~1559


A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic

Author(s):  ZENG Yong-hong, ZOU Xue-cheng, LIU Zheng-lin, LEI Jian-ming

Affiliation(s):  Research Center for VLSI and Systems, Department of Electronic Science & Technology, Huazhong University of Science & Technology, Wuhan 430074, China

Corresponding email(s):   zyher1974@126.com

Key Words:  Composite field, Rijndael S-Box, Full-custom, Pass transmission gate (PTG), Low power consumption, Low-voltage

ZENG Yong-hong, ZOU Xue-cheng, LIU Zheng-lin, LEI Jian-ming. A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic[J]. Journal of Zhejiang University Science A, 2007, 8(10): 1553~1559.

@article{title="A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic",
author="ZENG Yong-hong, ZOU Xue-cheng, LIU Zheng-lin, LEI Jian-ming",
journal="Journal of Zhejiang University Science A",
publisher="Zhejiang University Press & Springer",

%0 Journal Article
%T A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic
%A ZENG Yong-hong
%A ZOU Xue-cheng
%A LIU Zheng-lin
%A LEI Jian-ming
%J Journal of Zhejiang University SCIENCE A
%V 8
%N 10
%P 1553~1559
%@ 1673-565X
%D 2007
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.2007.A1553

T1 - A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic
A1 - ZENG Yong-hong
A1 - ZOU Xue-cheng
A1 - LIU Zheng-lin
A1 - LEI Jian-ming
J0 - Journal of Zhejiang University Science A
VL - 8
IS - 10
SP - 1553
EP - 1559
%@ 1673-565X
Y1 - 2007
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.2007.A1553

Using composite field arithmetic in Galois field can result in the compact rijndael S-Box. However, the power consumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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