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Received: 2007-03-09

Revision Accepted: 2007-04-27

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Journal of Zhejiang University SCIENCE A 2007 Vol.8 No.10 P.1553-1559


A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic

Author(s):  ZENG Yong-hong, ZOU Xue-cheng, LIU Zheng-lin, LEI Jian-ming

Affiliation(s):  Research Center for VLSI and Systems, Department of Electronic Science & Technology, Huazhong University of Science & Technology, Wuhan 430074, China

Corresponding email(s):   zyher1974@126.com

Key Words:  Composite field, Rijndael S-Box, Full-custom, Pass transmission gate (PTG), Low power consumption, Low-voltage

ZENG Yong-hong, ZOU Xue-cheng, LIU Zheng-lin, LEI Jian-ming. A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic[J]. Journal of Zhejiang University Science A, 2007, 8(10): 1553-1559.

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%A ZENG Yong-hong
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T1 - A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic
A1 - ZENG Yong-hong
A1 - ZOU Xue-cheng
A1 - LIU Zheng-lin
A1 - LEI Jian-ming
J0 - Journal of Zhejiang University Science A
VL - 8
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SP - 1553
EP - 1559
%@ 1673-565X
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.2007.A1553

Using composite field arithmetic in Galois field can result in the compact rijndael S-Box. However, the power consumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


[1] Bertoni, G., Macchetti, M., Negri, L., Fragneto, P., 2004. Power-efficient ASIC Synthesis of Cryptographic Sboxes. Proc. GLSVLSI, p.277-281.

[2] Canright, D., 2005. A very compact S-Box for AES. LNCS, 3659:441-455.

[3] Daemen, J., Rijmen, V., 2006. Understanding two-round differentials in AES. LNCS, 4116:78-94.

[4] Kuorilehto, M., Hannikainen, M., Hamalainen, T.D., 2005. A survey of application in wireless sensor networks. EURASIP J. Wirel. Commun. Networking, (5):774-788.

[5] Macchetti, M., Bertoni, G., 2002. Hardware implementation of the Rijndael S-BOX: a case study. ST J. Syst. Res., p.84-91.

[6] Mentens, N., Batina, L., Preneel, B., Verbauwhede, I., 2005. A systematic evaluation of compact hardware implementations for the Rijndael S-Box. LNCS, 3376:323-333.

[7] Morioka, S., Satoh, A., 2002. An optimized S-box circuit architecture for low power AES design. LNCS, 2523:172-186.

[8] Rudra, A., Dubey, P.K., Julta, C.S., Kumar, V., Rao, J.R., Rohatgi, P., 2001. Efficient Rijndael encryption implementation with composite field arithmetic. LNCS, 2162:171-184.

[9] Sasao, T., 1993. AND-EXOR Expressions and Their Optimization. Logic Synthesis and Optimization. Kluwer Academic Publishers, p.287-312.

[10] Satoh, A., Morioka, S., Takano, K., Munetoh, S., 2001. A compact Rijndael hardware architecture with S-Box optimization. LNCS, 2248:239-254.

[11] Suntiamorntut, W., 2005. Energy Efficient Functional Unit for a Parallel Asynchronous DSP. Ph.D Thesis, The University of Manchester, Manchester, UK.

[12] Tillich, S., Feldhofer, M., Großschädl, J., 2006. Area, delay, and power characteristics of standard-cell implementations of the AES S-Box. LNCS, 4017:457-466.

[13] Wolkerstorfer, J., Oswald, E., Lamberger, M., 2002. An ASIC implementation of the AES S-Boxes. LNCS, 2271:67-78.

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