Full Text:   <1510>

CLC number: TN402; TN47

On-line Access: 2010-06-02

Received: 2009-06-28

Revision Accepted: 2009-12-22

Crosschecked: 2010-05-04

Cited: 2

Clicked: 3461

Citations:  Bibtex RefMan EndNote GB/T7714

-   Go to

Article info.
1. Reference List
Open peer comments

Journal of Zhejiang University SCIENCE C 2010 Vol.11 No.6 P.444-449

http://doi.org/10.1631/jzus.C0910381


Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer


Author(s):  Di Li, Yin-tang Yang, Jiang-an Wang, Bing Li, Qiang Long, Jary Wei, Nai-di Wang, Lei Wang, Qian-kun Liu, Da-long Zhang

Affiliation(s):  School of Microelectronics, Xidian University, Xi’an 710071, China, Huaxun Microelectronics Corporation, Xi’an 710075, China

Corresponding email(s):   lidi2004@126.com

Key Words:  GPS receiver, Σ, Δ, fractional-N synthesizer, Image rejection, Phase noise


Di Li, Yin-tang Yang, Jiang-an Wang, Bing Li, Qiang Long, Jary Wei, Nai-di Wang, Lei Wang, Qian-kun Liu, Da-long Zhang. Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer[J]. Journal of Zhejiang University Science C, 2010, 11(6): 444-449.

@article{title="Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer",
author="Di Li, Yin-tang Yang, Jiang-an Wang, Bing Li, Qiang Long, Jary Wei, Nai-di Wang, Lei Wang, Qian-kun Liu, Da-long Zhang",
journal="Journal of Zhejiang University Science C",
volume="11",
number="6",
pages="444-449",
year="2010",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C0910381"
}

%0 Journal Article
%T Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer
%A Di Li
%A Yin-tang Yang
%A Jiang-an Wang
%A Bing Li
%A Qiang Long
%A Jary Wei
%A Nai-di Wang
%A Lei Wang
%A Qian-kun Liu
%A Da-long Zhang
%J Journal of Zhejiang University SCIENCE C
%V 11
%N 6
%P 444-449
%@ 1869-1951
%D 2010
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C0910381

TY - JOUR
T1 - Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer
A1 - Di Li
A1 - Yin-tang Yang
A1 - Jiang-an Wang
A1 - Bing Li
A1 - Qiang Long
A1 - Jary Wei
A1 - Nai-di Wang
A1 - Lei Wang
A1 - Qian-kun Liu
A1 - Da-long Zhang
J0 - Journal of Zhejiang University Science C
VL - 11
IS - 6
SP - 444
EP - 449
%@ 1869-1951
Y1 - 2010
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C0910381


Abstract: 
A 19 mW highly integrated GPS receiver with a Σ;Δ; fractional-N synthesizer is presented in this paper. Fractional-N frequency synthesizer architecture was adopted in this work, to provide more degrees of freedom in the synthesizer design. A high linearity low noise amplifier (LNA) is integrated into the chip. The radio receiver chip was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process and packaged in a 48-pin 2 mm×2 mm land grid array chip scale package. The chip consumes 19 mW (LNA1 excluded) and the LNA1 6.3 mW. Measured performances are: noise figure<2 dB, channel gain=108 dB (LNA1 included), image rejection>36 dB, and −108 dBc/Hz @ 1 MHz phase noise offset from the carrier. The carrier noise ratio (C/N) can reach 41 dB at an input power of −130 dBm. The chip operates over a temperature range of [−40, 120] °C and ±5% tolerance over the CMOS technology process.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

[1]Aloi, D.N., Alsliety, M., Akos, D.M., Rochester, M., 2007. A methodology for the evaluation of a GPS receiver performance in telematics applications. IEEE Trans. Instrum. Meas., 56(1):11-24.

[2]Bruzdzinski, J., Gronicz, J., Aaltonen, L., Halonen, K., 2008. Behavioral Simulation of Fractional-N PLL Frequency Synthesizers: Phase Approach. IEEE 11th Int. Biennial Baltic Electronics Conf., p.121-124.

[3]Chung, S.I., Lee, H.S., Lee, H.H., 2008. A Study on the In-Orbit Environment of a GPS Receiver for Low/Medium Altitude Satellites. 6th IEEE Int. Conf. on Industrial Informatics, p.694-699.

[4]Di, L., 2008. An Integrated GPS Receiver Front-End Design. China Patent ZL 200720032070.0 (in Chinese).

[5]Gramegna, G., Mattos, P.G., Losi, M., Das, S., Franciotta, M., Bellantone, N.G., Vaiana, M., Mandara, V., Paparo, M., 2006. A 56-mW 23-mm2 single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm2 radio. IEEE J. Sol.-State Circuits, 41(3):540-551.

[6]Huang, S.L., Ma, H.N., Wang, Z.H., 2007. Modeling and Simulation to the Design of Sigma-Delta Fractional-N Frequency Synthesizer. IEEE Design, Automation and Test in Europe Conf. and Exhibition, p.291-296.

[7]IEEE Global History Network, 2008. Citing IEEE org. IEEE Xplore Digital Library. Available from http://www.ieeeghn.org/wiki/index.php/Global_Positioning_System [Accessed on Apr. 30, 2009].

[8]Kim, J.M., Song, H.J., Kim, Y.B., 1999. Design and Implementation of L1-Band C/A-Code GPS RF Front-End Chip. 6th Int. Conf. on VLSI and CAD, p.372-375.

[9]Liu, L.Y., Amin, M.G., 2008. Performance analysis of GPS receivers in non-Gaussian noise incorporating precorrelation filter and sampling rate. IEEE Trans. Signal Process., 56(3):990-1004.

[10]Magoon, R., Molnar, A., Zachan, J., Hatcher, G., Rhee, W., 2002. A single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-N synthesizer. IEEE J. Sol.-State Circuits, 37(12):1710-1720.

[11]Peczalski, A., 2002. RF/Analog/Digital SOI Technology for GPS Receivers and Other Systems on a Chip. IEEE Aerospace Conf. Proc., 4:2013-2017.

[12]Rhee, W., Song, B.S., Ali, A., 2000. A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order (( modulator. IEEE J. Sol.-State Circuits, 35(10):1453-1458.

[13]Ti, C.H., Liu, Y.H., Lin, Y.H., 2008. A 2.4-GHz Fractional-N PLL with a PDF/CP Linearization and an Improved CP Circuit. IEEE Int. Symp. on Circuits and Systems, p.1728-1731.

[14]Tsui, J.B.Y., Akos, D.M., 1996. Comparison of Direct and Down-Converted Digitization in GPS Receiver Front End Designs. Microwave Symp. Digest, IEEE MTT-S Int., 3:1343-1346.

[15]Wang, E.S., Zhang, S.F., Hu, Q., Yi, J., Sun, X.W., 2008. Implementation of an Embedded GPS Receiver Based on FPGA and Micro Blaze. 4th IEEE Int. Conf. on Wireless Communications, Networking and Mobile Computing, p.1-4.

[16]Xiao, P., Thomsen, A., Abraham, J., 2008. Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL. IEEE Computer Society Annual Symp. on VLSI, p.168-172.

[17]Zhu, Y.H., Shao, Z.B., Pang, W.Y., 2004. A generalized MASH architecture in fractional-N synthesizer. IEEE J. Sol.-State Circuits, 2:1512-1515.

Open peer comments: Debate/Discuss/Question/Opinion

<1>

Please provide your name, email address and a comment





Journal of Zhejiang University-SCIENCE, 38 Zheda Road, Hangzhou 310027, China
Tel: +86-571-87952783; E-mail: cjzhang@zju.edu.cn
Copyright © 2000 - Journal of Zhejiang University-SCIENCE