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CLC number: TN919.8

On-line Access: 2011-06-07

Received: 2010-06-16

Revision Accepted: 2011-02-17

Crosschecked: 2011-05-05

Cited: 3

Clicked: 3358

Citations:  Bibtex RefMan EndNote GB/T7714

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Journal of Zhejiang University SCIENCE C 2011 Vol.12 No.6 P.499-506


An efficient hardware design for HDTV H.264/AVC encoder

Author(s):  Liang Wei, Dan-dan Ding, Juan Du, Bin-bin Yu, Lu Yu

Affiliation(s):  Institute of Information and Communication Engineering, Zhejiang University, Hangzhou 310027, China, Zhejiang Provincial Key Laboratory of Information Network Technology, Hangzhou 310027, China

Corresponding email(s):   weiliang33@126.com, yul@zju.edu.cn

Key Words:  H.264/AVC, High-definition television (HDTV), Hardware, Architecture, Encoder

Liang Wei, Dan-dan Ding, Juan Du, Bin-bin Yu, Lu Yu. An efficient hardware design for HDTV H.264/AVC encoder[J]. Journal of Zhejiang University Science C, 2011, 12(6): 499-506.

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This paper presents a hardware efficient high definition television (HDTV) encoder for h.264/AVC. We use a two-level mode decision (MD) mechanism to reduce the complexity and maintain the performance, and design a sharable architecture for normal mode fractional motion estimation (NFME), special mode fractional motion estimation (SFME), and luma motion compensation (LMC), to decrease the hardware cost. Based on these technologies, we adopt a four-stage macro-block pipeline scheme using an efficient memory management strategy for the system, which greatly reduces on-chip memory and bandwidth requirements. The proposed encoder uses about 1126k gates with an average Bjontegaard-Delta peak signal-to-noise ratio (BD-PSNR) decrease of 0.5 dB, compared with JM15.0. It can fully satisfy the real-time video encoding for 1080p@30 frames/s of h.264/AVC high profile.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


[1]Chang, T.C., Chen, J.W., Su, C.L., Yang, Y.C., Li, Y., Chang, C.H., Chen, Z.M., Yang, W.S., Lin, C.C., Chen, C.W., et al., 2007. A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip. IEEE Int. Solid-State Circuits Conf., p.280-281.

[2]Chen, T.C., Chien, S.Y., Huang, Y.W., Tsai, C.H., Chen, C.Y., Chen, T.W., Chen, L.G., 2006. Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder. IEEE Trans. Circ. Syst. Video Technol., 16(6):673-688.

[3]Chen, Y.H., Chuang, T.D., Chen, Y.J., Li, C.T., Hsu, C.J., Chien, S.Y., Chen, L.G., 2008. An H.264/AVC Scalable Extension and High Profile HDTV 1080p Encoder Chip. IEEE Symp. on VLSI Circuits, p.104-105.

[4]Huang, Y.W., Chen, T.C., Tsai, C.H., Chen, C.Y., Chen, T.W., Chen, C.S., Shen, C.F., Ma, S.Y., Wang, T.C., Hsieh, B.Y., et al., 2005. A 1.3TOPS H.264/AVC Single-Chip Encoder for HDTV Applications. IEEE Int. Solid-State Circuits Conf., p.128-133.

[5]ITU-T, 2005. ITU-T Recommendation and International Standard of Joint Video Specification. H.264/ISO/IEC 14496-10 AVC.

[6]Lee, K.H., Alshina, E., Park, J.H., Han, W.J., Min, J.H., 2008. Technical Considerations for Ad Hoc Group on New Challenges in Video Coding Standardization. MPEG Doc. M15580. Hannover, Germany.

[7]Lin, Y.K., Lin, C.C., Kuo, T.Y., Chang, T.S., 2008a. A hardware-efficient H.264/AVC motion-estimation design for high-definition video. IEEE Trans. Circ. Syst. I, 55(6):1526-1535.

[8]Lin, Y.K., Li, D.W., Lin, C.C., Kuo, T.Y., Wu, S.J., Tai, W.C., Chang, W.C., Chang, T.S., 2008b. A 242mW, 10mm2 1080p H.264/AVC High Profile Encoder Chip. 45th ACM/IEEE Design Automation Conf., p.78-83.

[9]Liu, Z.Y., Song, Y., Shao, M., Li, S., Li, L.Y., Ishiwata, S., Nakagawa, M., Goto, S., Ikenaga, T., 2009. HDTV1080p H.264/AVC encoder chip design and performance analysis. IEEE J. Sol.-State Circ., 44(2):594-608.

[10]Park, S.H., Lee, J.H., 2008. Hardware Architecture for Real-Time HD(1920×1080@60fps) H.264/AVC Intra Prediction. IEEE Int. Symp. on Consumer Electronics, p.1.

[11]Wiegand, T., Schwarz, H., Joch, A., Kossentini, F., Sullivan, G.J., 2003. Rate-constrained coder control and comparison of video coding standards. IEEE Trans. Circ. Syst. Video Technol., 13(7):688-703.

[12]Yang, C.Q., Goto, S., Ikenaga, T., 2006. High Performance VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV. Proc. IEEE Int. Symp. on Circuits and Systems, p.1-4.

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