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CLC number: TN91

On-line Access: 2010-01-10

Received: 2010-07-02

Revision Accepted: 2010-10-11

Crosschecked: 2010-12-08

Cited: 12

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Journal of Zhejiang University SCIENCE C 2011 Vol.12 No.1 P.76-82


A pipelined architecture for normal I/O order FFT

Author(s):  Xue Liu, Feng Yu, Ze-ke Wang

Affiliation(s):  Department of Instrument Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   liuxue0412@tom.com, osfengyu@zju.edu.cn

Key Words:  Fast Fourier transform (FFT), Single-path delay commutator (SDC), Pipelined FFT, Bit reverser

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Xue Liu, Feng Yu, Ze-ke Wang. A pipelined architecture for normal I/O order FFT[J]. Journal of Zhejiang University Science C, 2011, 12(1): 76-82.

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%DOI 10.1631/jzus.C1000234

T1 - A pipelined architecture for normal I/O order FFT
A1 - Xue Liu
A1 - Feng Yu
A1 - Ze-ke Wang
J0 - Journal of Zhejiang University Science C
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SP - 76
EP - 82
%@ 1869-1951
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.C1000234

We present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

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[1]Bi, G., Jones, E.V., 1989. A pipelined FFT processor for word-sequential data. IEEE Trans. Acoust. Speech Signal Process., 37(12):1982-1985.

[2]Chang, Y.N., 2008. An efficient VLSI architecture for normal I/O order pipeline FFT design. IEEE Trans. Circ. Syst. II: Exp. Briefs, 55(12):1234-1238.

[3]Cheng, C., Parhi, K.K., 2007. High-throughput VLSI architecture for FFT computation. IEEE Trans. Circ. Syst. II: Exp. Briefs, 54(10):863-867.

[4]Cortes, A., Velez, I., Sevillano, J.F., 2009. Radix rk FFTs: matricial representation and SDC/SDF pipeline implementation. IEEE Trans. Signal Process., 57(7):2824-2839.

[5]Despain, A.M., 1974. Fourier transform computer using CORDIC iterations. IEEE Trans. Comput., c-23(10):993-1001.

[6]Garrido, M., Parhi, K.K., Grajal, J., 2009. A pipelined FFT architecture for real-valued signals. IEEE Trans. Circ. Syst. I: Reg. Papers, 56(12):2634-2643.

[7]He, S., Torkelson, M., 1996. A New Approach to Pipeline FFT Processor. Proc. 10th Int. Symp. on Parallel Processing, p.766-770.

[8]Lin, Y.W., Liu, H.Y., Lee, C.Y., 2005. A 1-GS/s FFT/IFFT processor for UWB applications. IEEE J. Sol.-State Circ., 40(8):1726-1735.

[9]Oh, J.Y., Lim, M.S., 2005. Area and Power Efficient Pipeline FFT Algorithm. Proc. IEEE Workshop on Signal Processing System Design and Implementation, p.520-525.

[10]Rabiner, L.R., Gold, B., 1975. Theory and Application of Digital Signal Processing. Prentice-Hall, Inc., USA, p.604-609.

[11]Sansaloni, T., Perez-Pascual, A., Torres, V., Valls, J., 2005. Efficient pipeline FFT processors for WLAN MIMO-OFDM systems. Electron. Lett., 41(19):1043-1044.

[12]Sung, T.Y., Hsin, H.C., Cheng, Y.P., 2010. Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems. Dig. Signal Process., 20(2):511-527.

[13]Swartzlander, E.E., Young, W.K.W., Joseph, S.J., 1984. A radix 4 delay commutator for fast Fourier transforms processor implementation. IEEE J. Sol.-State Circ., 19(5):702-709.

[14]Wold, E.H., Despain, A.M., 1984. Pipeline and parallel-pipeline FFT processors for VLSI implementation. IEEE Trans. Comput., c-33(5):414-426.

[15]Yeh, W.C., Jen, C.W., 2003. High-speed and low-power split-radix FFT. IEEE Trans. Signal Process., 51(3):864-874.

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