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CLC number: TN91

On-line Access: 2011-04-11

Received: 2010-07-21

Revision Accepted: 2011-01-06

Crosschecked: 2011-02-28

Cited: 1

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Journal of Zhejiang University SCIENCE C 2011 Vol.12 No.4 P.323-329

http://doi.org/10.1631/jzus.C1000258


An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays


Author(s):  Zhen-guo Ma, Feng Yu, Rui-feng Ge, Ze-ke Wang

Affiliation(s):  Department of Instrument Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   mzgzju@yahoo.com.cn, osfengyu@zju.edu.cn

Key Words:  Ganged butterfly engine (GBE), Radix-2, Fast Fourier transform (FFT), Field programmable gate array (FPGA)


Zhen-guo Ma, Feng Yu, Rui-feng Ge, Ze-ke Wang. An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays[J]. Journal of Zhejiang University Science C, 2011, 12(4): 323-329.

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T1 - An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays
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DOI - 10.1631/jzus.C1000258


Abstract: 
We present a novel method to implement the radix-2 fast Fourier transform (FFT) algorithm on field programmable gate arrays (FPGA). The FFT architecture exploits parallelism by having more pipelined units in the stages, and more parallel units within a stage. It has the noticeable advantages of high speed and more efficient resource utilization by employing four ganged butterfly engines (GBEs), and can be well matched to the placement of the resources on the FPGA. We adopt the decimation-in-frequency (DIF) radix-2 FFT algorithm and implement the FFT processor on a state-of-the-art FPGA. Experimental results show that the processor can compute 1024-point complex radix-2 FFT in about 11 μs with a clock frequency of 200 MHz.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

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[5]Garrido, M., Parhi, K.K., Grajal, J., 2009. A pipelined FFT architecture for real-valued signals. IEEE Trans. Circ. Syst. I: Reg. Papers, 56(12):2634-2643.

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[8]Kee, H., Bhattacharyya, S.S., Petersen, N., Kornerup, J., 2009. Resource-Efficient Acceleration of 2-Dimensional Fast Fourier Transform Computations on FPGAs. Third ACM/IEEE Int. Conf. on Distributed Smart Cameras, p.1-8.

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[11]Radhouane, R., Liu, P., Modlin, C., 2000. Minimizing the Memory Requirement for Continuous Flow FFT Implementation: Continuous Flow Mixed Mode FFT (CFMM-FFT). Proc. IEEE Int. Symp. on Circuits and Systems, 1:116-119.

[12]Sun, T.Y., Yu, Y.H., 2009. Memory Usage Reduction Method for FFT Implementations on DSP Based Embedded System. IEEE 13th Int. Symp. on Consumer Electronics, p.812-815.

[13]Thoen, D.J., Bongers, W.A., Westerhof, E., Oosterbeek, J.W., de Baar, M.R., van den Berg, M.A., van Beveren, V., Burger, A., Goede, A., Graswinckel, M.F., et al., 2009. Fast Fourier Transform Based Diagnostics for Spectral Characterization of Millimeter Waves in Tokamaks. 34th Int. Conf. on Infrared, Millimeter, and Terahertz Waves, p.1-2.

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