CLC number: TN91
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2011-02-28
Cited: 1
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Zhen-guo Ma, Feng Yu, Rui-feng Ge, Ze-ke Wang. An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays[J]. Journal of Zhejiang University Science C, 2011, 12(4): 323-329.
@article{title="An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays",
author="Zhen-guo Ma, Feng Yu, Rui-feng Ge, Ze-ke Wang",
journal="Journal of Zhejiang University Science C",
volume="12",
number="4",
pages="323-329",
year="2011",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C1000258"
}
%0 Journal Article
%T An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays
%A Zhen-guo Ma
%A Feng Yu
%A Rui-feng Ge
%A Ze-ke Wang
%J Journal of Zhejiang University SCIENCE C
%V 12
%N 4
%P 323-329
%@ 1869-1951
%D 2011
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1000258
TY - JOUR
T1 - An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays
A1 - Zhen-guo Ma
A1 - Feng Yu
A1 - Rui-feng Ge
A1 - Ze-ke Wang
J0 - Journal of Zhejiang University Science C
VL - 12
IS - 4
SP - 323
EP - 329
%@ 1869-1951
Y1 - 2011
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1000258
Abstract: We present a novel method to implement the radix-2 fast Fourier transform (FFT) algorithm on field programmable gate arrays (FPGA). The FFT architecture exploits parallelism by having more pipelined units in the stages, and more parallel units within a stage. It has the noticeable advantages of high speed and more efficient resource utilization by employing four ganged butterfly engines (GBEs), and can be well matched to the placement of the resources on the FPGA. We adopt the decimation-in-frequency (DIF) radix-2 FFT algorithm and implement the FFT processor on a state-of-the-art FPGA. Experimental results show that the processor can compute 1024-point complex radix-2 FFT in about 11 μs with a clock frequency of 200 MHz.
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