Full Text:   <2305>

CLC number: TN915.05

On-line Access: 2011-11-30

Received: 2011-03-26

Revision Accepted: 2011-08-16

Crosschecked: 2011-11-04

Cited: 4

Clicked: 3149

Citations:  Bibtex RefMan EndNote GB/T7714

-   Go to

Article info.
1. Reference List
Open peer comments

Journal of Zhejiang University SCIENCE C 2011 Vol.12 No.12 P.1021-1030

http://doi.org/10.1631/jzus.C1100071


A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system


Author(s):  Ji-nan Leng, Lei Xie, Hui-fang Chen, Kuang Wang

Affiliation(s):  Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China, Zhejiang Provincial Key Laboratory of Information Network Technology, Hangzhou 310027, China

Corresponding email(s):   xiel@zju.edu.cn

Key Words:  3780, CoOrdinate Rotation DIgital Computer (CORDIC), Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T), FFT, Time domain synchronous OFDM (TDS-OFDM), Winograd Fourier transform algorithm (WFTA)


Share this article to: More <<< Previous Article|

Ji-nan Leng, Lei Xie, Hui-fang Chen, Kuang Wang. A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system[J]. Journal of Zhejiang University Science C, 2011, 12(12): 1021-1030.

@article{title="A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system",
author="Ji-nan Leng, Lei Xie, Hui-fang Chen, Kuang Wang",
journal="Journal of Zhejiang University Science C",
volume="12",
number="12",
pages="1021-1030",
year="2011",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C1100071"
}

%0 Journal Article
%T A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system
%A Ji-nan Leng
%A Lei Xie
%A Hui-fang Chen
%A Kuang Wang
%J Journal of Zhejiang University SCIENCE C
%V 12
%N 12
%P 1021-1030
%@ 1869-1951
%D 2011
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1100071

TY - JOUR
T1 - A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system
A1 - Ji-nan Leng
A1 - Lei Xie
A1 - Hui-fang Chen
A1 - Kuang Wang
J0 - Journal of Zhejiang University Science C
VL - 12
IS - 12
SP - 1021
EP - 1030
%@ 1869-1951
Y1 - 2011
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1100071


Abstract: 
The 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system and the key technology in the Chinese digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. Since 3780 is not a power of 2, the classical radix-2 or radix-4 FFT algorithm cannot be applied directly. Hence, the winograd Fourier transform algorithm (WFTA) and the Good-Thomas prime factor algorithm (PFA) are used to implement the 3780-point FFT processor. However, the structure based on WFTA and PFA has a large computational complexity and requires many DSPs in hardware implementation. In this paper, a novel 3780-point FFT processor scheme is proposed, in which a 60(63 iterative WFTA architecture with different mapping methods is imported to replace the PFA architecture, and an optimized coOrdinate Rotation DIgital Computer (CORDIC) module is used for the twiddle factor multiplications. Compared to the traditional scheme, our proposed 3780-point FFT processor scheme reduces the number of multiplications by 45% at the cost of 1% increase in the number of additions. All DSPs are replaced by the optimized CORDIC module and ROM. Simulation results show that the proposed 3780-point FFT processing scheme satisfies the requirement of the DMB-T standard, and is an efficient architecture for the TDS-OFDM system.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

[1]Abdullah, S., Haewoon, N., McDermot, M., Abraham, J., 2009. A High Throughput FFT Processor with No Multipliers. IEEE Int. Conf. on Computer Design, p.485-490.

[2]Adiono, T., Purba, R.S., 2009. Scalable Pipelined CORDIC Architecture Design and Implementation in FPGA. Int. Conf. on Electrical Engineering and Informatics, p.646-649.

[3]Camarda, F., Prevotet, J.C., Nouvel, F., 2009. Implementation of a Reconfigurable Fast Fourier Transform Application to Digital Terrestrial Television Broadcasting. 19th Int. Conf. on Field Programmable Logic and Applications, p.353-358.

[4]Cheng, C., Parhi, K.K., 2007. Low-cost fast VLSI algorithm for discrete Fourier transform. IEEE Trans. Circ. Syst. I, 54(4):791-806.

[5]Cheng, G., Su, K., 2010. A 3780-point FFT Algorithm and Its FPGA Implementation. Int. Symp. on Next Generation Electronics, p.231-233.

[6]Cooley, J.W., Tukey, J.W., 1965. An algorithm for the machine calculation of complex Fourier series. Math. Comput., 19(90):297-301.

[7]Good, I.J., 1958. The interaction algorithm and practical Fourier series. J. R. Stat. Soc., 20(2):361-372.

[8]Lakshmi, B., Dhar, A.S., 2008. Low Latency VLSI Architecture for the Radix-4 CORDIC Algorithm. IEEE Region 10 and 3rd Int. Conf. on Industrial and Information Systems, p.1-5.

[9]Liu, M., Crussiere, M., Helard, J.F., Pasquero, O.P., 2008. Analysis and Performance Comparison of DVB-T and DTMB Systems for Terrestrial Digital TV. 11th IEEE Int. Conf. on Communication Systems, p.1399-1404.

[10]Patterson, R.W., Mcclellan, J.H., 1978. Fixed-point error analysis of Winograd Fourier transform algorithms. IEEE Trans. Acoust. Speech Signal Process., 26(5):447-455.

[11]SAC (Standardization Administration of the People’s Republic of China), 2006. Framing Structure, Channel Coding and Modulation for Digital Television Terrestrial Broadcasting System. Standards Press of China, Beijing, China (in Chinese).

[12]Silverman, H., 1977. An introduction to programming the Winograd Fourier transform algorithm (WFTA). IEEE Trans. Acoust. Speech Signal Process., 25(2):152-165.

[13]Song, J., Yang, Z., Yang, L., Gong, K., Pan, C., Wang, J., Wu, Y., 2007. Technical review on Chinese Digital Terrestrial Television Broadcasting Standard and measurements on some working modes. IEEE Trans. Broadcast., 53(1):1-7.

[14]Volder, J.E., 1959. The CORDIC trigonometric computing technique. IEEE Trans. Electron. Comput., 8(3):330-334.

[15]Winograd, S., 1976. On computing the discrete Fourier transform. PNAS, 73(4):1005-1006.

[16]Wu, C., Wang, R., Yen, C., 1994. Adder-based SIMD-systolic architectures and VLSI chip for computing the Winograd small FFT algorithms. Int. J. Electron., 76(6):1135-1149.

[17]Xing, Q., Zhu, Q., Sun, S., 1996. Iterative Structure of Winograd FFT Algorithm. Conf. on Precision Electromagnetic Measurements, p.57-58.

[18]Yang, J., Wang, K., Zou, Z., 2007. DVB-S2 inner receiver design for broadcasting mode. J. Zhejiang Univ.-Sci. A, 8(1):28-35.

[19]Yang, X., Du, W., Yang, Z., Lv, R., Wang, X., 2010. Hardware Design and Implementation of 3780 Points FFT Based on FPGA in DTTB. 4th Int. Conf. on Application of Information and Communication Technologies, p.1-4.

[20]Yang, Z., Hu, Y., Pan, C., Yang, L., 2002. Design of a 3780-point IFFT processor for TDS-OFDM. IEEE Trans. Broadcast., 48(1):57-61.

Open peer comments: Debate/Discuss/Question/Opinion

<1>

Please provide your name, email address and a comment





Journal of Zhejiang University-SCIENCE, 38 Zheda Road, Hangzhou 310027, China
Tel: +86-571-87952783; E-mail: cjzhang@zju.edu.cn
Copyright © 2000 - Journal of Zhejiang University-SCIENCE