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CLC number: TN915.05

On-line Access: 2011-11-30

Received: 2011-03-26

Revision Accepted: 2011-08-16

Crosschecked: 2011-11-04

Cited: 4

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Journal of Zhejiang University SCIENCE C 2011 Vol.12 No.12 P.1021-1030


A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system

Author(s):  Ji-nan Leng, Lei Xie, Hui-fang Chen, Kuang Wang

Affiliation(s):  Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China, Zhejiang Provincial Key Laboratory of Information Network Technology, Hangzhou 310027, China

Corresponding email(s):   xiel@zju.edu.cn

Key Words:  3780, CoOrdinate Rotation DIgital Computer (CORDIC), Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T), FFT, Time domain synchronous OFDM (TDS-OFDM), Winograd Fourier transform algorithm (WFTA)

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Ji-nan Leng, Lei Xie, Hui-fang Chen, Kuang Wang. A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system[J]. Journal of Zhejiang University Science C, 2011, 12(12): 1021-1030.

@article{title="A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system",
author="Ji-nan Leng, Lei Xie, Hui-fang Chen, Kuang Wang",
journal="Journal of Zhejiang University Science C",
publisher="Zhejiang University Press & Springer",

%0 Journal Article
%T A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system
%A Ji-nan Leng
%A Lei Xie
%A Hui-fang Chen
%A Kuang Wang
%J Journal of Zhejiang University SCIENCE C
%V 12
%N 12
%P 1021-1030
%@ 1869-1951
%D 2011
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1100071

T1 - A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system
A1 - Ji-nan Leng
A1 - Lei Xie
A1 - Hui-fang Chen
A1 - Kuang Wang
J0 - Journal of Zhejiang University Science C
VL - 12
IS - 12
SP - 1021
EP - 1030
%@ 1869-1951
Y1 - 2011
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1100071

The 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system and the key technology in the Chinese digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. Since 3780 is not a power of 2, the classical radix-2 or radix-4 FFT algorithm cannot be applied directly. Hence, the winograd Fourier transform algorithm (WFTA) and the Good-Thomas prime factor algorithm (PFA) are used to implement the 3780-point FFT processor. However, the structure based on WFTA and PFA has a large computational complexity and requires many DSPs in hardware implementation. In this paper, a novel 3780-point FFT processor scheme is proposed, in which a 60(63 iterative WFTA architecture with different mapping methods is imported to replace the PFA architecture, and an optimized coOrdinate Rotation DIgital Computer (CORDIC) module is used for the twiddle factor multiplications. Compared to the traditional scheme, our proposed 3780-point FFT processor scheme reduces the number of multiplications by 45% at the cost of 1% increase in the number of additions. All DSPs are replaced by the optimized CORDIC module and ROM. Simulation results show that the proposed 3780-point FFT processing scheme satisfies the requirement of the DMB-T standard, and is an efficient architecture for the TDS-OFDM system.

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