
Ping LV, Qinrang LIU, Jiangxing WU, Jianliang SHEN, Mengke LIAN, Rui CAO, Shuai WEI, Zhichao LI, Peijie LI, Wei GUO, Wenjian ZHANG, Hong YU, Yanzhao GAO. From software-defined interconnect to software-defined system-on-wafer: a computing architecture revolution in the post-Moore era[J]. Journal of Zhejiang University Science C, 2026, 27(5): 1-13.
@article{title="From software-defined interconnect to software-defined system-on-wafer: a computing architecture revolution in the post-Moore era",
author="Ping LV, Qinrang LIU, Jiangxing WU, Jianliang SHEN, Mengke LIAN, Rui CAO, Shuai WEI, Zhichao LI, Peijie LI, Wei GUO, Wenjian ZHANG, Hong YU, Yanzhao GAO",
journal="Journal of Zhejiang University Science C",
volume="27",
number="5",
pages="1-13",
year="2026",
publisher="Zhejiang University Press & Springer",
doi="10.1631/ENG.ITEE.2025.0063"
}
%0 Journal Article
%T From software-defined interconnect to software-defined system-on-wafer: a computing architecture revolution in the post-Moore era
%A Ping LV
%A Qinrang LIU
%A Jiangxing WU
%A Jianliang SHEN
%A Mengke LIAN
%A Rui CAO
%A Shuai WEI
%A Zhichao LI
%A Peijie LI
%A Wei GUO
%A Wenjian ZHANG
%A Hong YU
%A Yanzhao GAO
%J Frontiers of Information Technology & Electronic Engineering
%V 27
%N 5
%P 1-13
%@ 1869-1951
%D 2026
%I Zhejiang University Press & Springer
%DOI 10.1631/ENG.ITEE.2025.0063
TY - JOUR
T1 - From software-defined interconnect to software-defined system-on-wafer: a computing architecture revolution in the post-Moore era
A1 - Ping LV
A1 - Qinrang LIU
A1 - Jiangxing WU
A1 - Jianliang SHEN
A1 - Mengke LIAN
A1 - Rui CAO
A1 - Shuai WEI
A1 - Zhichao LI
A1 - Peijie LI
A1 - Wei GUO
A1 - Wenjian ZHANG
A1 - Hong YU
A1 - Yanzhao GAO
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 27
IS - 5
SP - 1
EP - 13
%@ 1869-1951
Y1 - 2026
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/ENG.ITEE.2025.0063
Abstract: As Moore’s law approaches its fundamental physical and economic limits, the semiconductor industry faces unprecedented challenges in maintaining performance growth. This study presents the revolutionary evolution from software-defined interconnect (SDI) to software-defined system-on-wafer (SDSoW), a paradigm-shifting architectural approach that transcends traditional scaling constraints through wafer-level heterogeneous integration. Our proposed SDSoW enables dynamic reconfiguration of thousands of computing chiplets across an entire wafer, achieving superlinear performance scaling and significantly improving energy efficiency. We establish a comprehensive theoretical framework with mathematical models covering key aspects, such as interconnect flexibility and integration scaling, and propose an application-driven dynamic architecture reconfiguration (ADR) paradigm that optimizes wafer-scale resources in real time and may foster emergent intelligence in large, heterogeneous systems. Simulation results (128–1024 nodes) demonstrate that SDSoW outperforms conventional multi-chip systems, delivering approximately 3.73×–4.39× higher throughput, 79.2% lower latency, and 2.8 × higher power efficiency. As a paradigm shift comparable to the invention of integrated circuits (ICs), it provides a viable pathway beyond Moore’s law through innovative architectural design rather than process scaling.
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CLC number: TP303
On-line Access: 2026-05-27
Received: 2025-09-30
Revision Accepted: 2026-03-13
Crosschecked: 2026-05-27
Cited: 0
Clicked: 850
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