ENGINEERING Information Technology & Electronic Engineering  2026 Vol.27 No.5 P.1-13

http://doi.org/10.1631/ENG.ITEE.2025.0063


From software-defined interconnect to software-defined system-on-wafer: a computing architecture revolution in the post-Moore era


Author(s):  Ping LV, Qinrang LIU, Jiangxing WU, Jianliang SHEN, Mengke LIAN, Rui CAO, Shuai WEI, Zhichao LI, Peijie LI, Wei GUO, Wenjian ZHANG, Hong YU, Yanzhao GAO

Affiliation(s):  1. Information Engineering University, Zhengzhou 450001, China more

Corresponding email(s):   qinrangliu@sina.com

Key Words:  Software-defined interconnect (SDI), Software-defined system-on-wafer (SDSoW), Wafer-level integration, Emergent intelligence, Heterogeneous computing


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Ping LV, Qinrang LIU, Jiangxing WU, Jianliang SHEN, Mengke LIAN, Rui CAO, Shuai WEI, Zhichao LI, Peijie LI, Wei GUO, Wenjian ZHANG, Hong YU, Yanzhao GAO. From software-defined interconnect to software-defined system-on-wafer: a computing architecture revolution in the post-Moore era[J]. Journal of Zhejiang University Science C, 2026, 27(5): 1-13.

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author="Ping LV, Qinrang LIU, Jiangxing WU, Jianliang SHEN, Mengke LIAN, Rui CAO, Shuai WEI, Zhichao LI, Peijie LI, Wei GUO, Wenjian ZHANG, Hong YU, Yanzhao GAO",
journal="Journal of Zhejiang University Science C",
volume="27",
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pages="1-13",
year="2026",
publisher="Zhejiang University Press & Springer",
doi="10.1631/ENG.ITEE.2025.0063"
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%A Mengke LIAN
%A Rui CAO
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%A Zhichao LI
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%A Wei GUO
%A Wenjian ZHANG
%A Hong YU
%A Yanzhao GAO
%J Frontiers of Information Technology & Electronic Engineering
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A1 - Jianliang SHEN
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A1 - Zhichao LI
A1 - Peijie LI
A1 - Wei GUO
A1 - Wenjian ZHANG
A1 - Hong YU
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Abstract: 
As Moore’s law approaches its fundamental physical and economic limits, the semiconductor industry faces unprecedented challenges in maintaining performance growth. This study presents the revolutionary evolution from software-defined interconnect (SDI) to software-defined system-on-wafer (SDSoW), a paradigm-shifting architectural approach that transcends traditional scaling constraints through wafer-level heterogeneous integration. Our proposed SDSoW enables dynamic reconfiguration of thousands of computing chiplets across an entire wafer, achieving superlinear performance scaling and significantly improving energy efficiency. We establish a comprehensive theoretical framework with mathematical models covering key aspects, such as interconnect flexibility and integration scaling, and propose an application-driven dynamic architecture reconfiguration (ADR) paradigm that optimizes wafer-scale resources in real time and may foster emergent intelligence in large, heterogeneous systems. Simulation results (128–1024 nodes) demonstrate that SDSoW outperforms conventional multi-chip systems, delivering approximately 3.73×–4.39× higher throughput, 79.2% lower latency, and 2.8 × higher power efficiency. As a paradigm shift comparable to the invention of integrated circuits (ICs), it provides a viable pathway beyond Moore’s law through innovative architectural design rather than process scaling.

从软件定义互连到软件定义晶圆级系统:后摩尔时代的计算架构革命

吕平1,刘勤让2,邬江兴3,沈剑良1,连梦珂1,曹睿1,魏帅1,李智超1,李沛杰1,郭威1,张文建1,于洪1,高彦钊1
1信息工程大学,中国郑州市,450001
2复旦大学大数据研究院,中国上海市,200433
3国家数字交换系统工程技术研究中心,中国郑州市,450002
摘要:随着摩尔定律逼近其物理与经济层面的根本极限,半导体行业在维持性能增长方面面临前所未有的挑战。本研究阐述了从软件定义互连(SDI)到软件定义晶圆级系统(SDSoW)的革命性演进;SDSoW这一颠覆性架构方案通过晶圆级异质集成突破了传统缩放约束。本文提出的SDSoW可在整片晶圆上实现数千个计算小芯片的动态重构,实现超线性性能缩放,并显著提升能效。我们构建了一个综合理论框架,涵盖了互连灵活性、集成缩放等关键维度的数学模型,并提出一种应用驱动的动态架构重构(ADR)方案,该方案可实时优化晶圆级资源配置,并有望在大规模异质系统中催生涌现智能。基于128–1024个节点的仿真结果表明,SDSoW优于传统多芯片系统,其吞吐量提升约3.73–4.39倍,延迟降低约79.2%,能效提升约2.8倍。作为一项堪比集成电路(IC)发明的技术变革,该方案不依赖工艺微缩,而是通过创新的架构设计,为突破摩尔定律提供一条可行路径。

关键词:软件定义互连(SDI);软件定义晶圆级系统(SDSoW);晶圆级集成;涌现智能;异构计算

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Reference

[1]Attig M, Brebner G, 2011. 400 Gb/s programmable packet parsing on a single FPGA. ACM/IEEE Seventh Symp on Architectures for Networking and Communications Systems, p.12-23.

[2]Balandin AA, 2020. Phononics of graphene and related materials. ACS Nano, 14(5):5170-5178.

[3]Behnam A, Sangwan VK, Zhong XY, et al., 2013. High-field transport and thermal reliability of sorted carbon nanotube network devices. ACS Nano, 7(1):482-490.

[4]Berestizshevsky K, Even G, Fais Y, et al., 2017. SDNoC: software defined network on a chip. Microprocess Microsyst, 50:138-153.

[5]Cerebras Systems Inc., 2019. Wafer-Scale Deep Learning. IEEE Hot Chips 31 Symp, p.1-31.

[6]Chen KN, 2023. Hybrid bonding: the key technology to reach fine pitch and high density stacking in heterogeneous integration. Int VLSI Symp on Technology, Systems and Applications, p.1.

[7]Chew SA, De Vos J, Beyne E, 2024. Wafer-to-wafer hybrid bonding at 400-nm interconnect pitch. Nat Rev Electr Eng, 1(2):71-72.

[8]Deshmukh PK, Mane DT, 2023. QoS-aware routing and resource allocation techniques for enhanced network performance. J Electr Syst, 19(2):78-86.

[9]Gomez-Rodriguez JR, Sandoval-Arechiga R, Ibarra-Delgado S, et al., 2021. A survey of software-defined networks-on-chip: motivations, challenges and opportunities. Micromachines, 12(2):183.

[10]Gonzalez-Martinez G, Sandoval-Arechiga R, Solis-Sanchez LO, et al., 2024. A survey of MPSoC management toward self-awareness. Micromachines, 15(5):577.

[11]Goossens K, Koedam M, Nelson A, et al., 2017. NoC-based multiprocessor architecture for mixed-time-criticality applications. In: Ha S, Teich J (Eds.), Handbook of Hardware/Software Codesign. Springer, Dordrecht, p.491-530.

[12]Hall S, Schreiber R, Lie S, et al., 2021. Training giant neural networks using weight streaming on Cerebras wafer-scale systems. https://www.kisacoresearch.com/sites/default/files/documents/cs_weight_streaming_white_paper_-_cerebras.pdf [Accessed on Sept. 30, 2025].

[13]Ham TJ, Wu LS, Sundaram N, et al., 2016. Graphicionado: a high-performance and energy-efficient accelerator for graph analytics. 49th Annual IEEE/ACM Int Symp on Microarchitecture, p.1-13.

[14]Huang SH, Waeijen L, Corporaal H, 2022. How flexible is your computing system? ACM Trans Embed Comput Syst, 21(4):37.

[15]Ji N, Zhou XF, Yang YT, 2023. A high-performance fully adaptive routing based on software defined network-on-chip. Microelectron J, 141:105950.

[16]Kerrison S, May D, Eder K, 2016. A Benes based NoC switching architecture for mixed criticality embedded systems. IEEE 10th Int Symp on Embedded Multicore/Many-Core Systems-on-Chip, p.125-132.

[17]Khan HN, Hounshell DA, Fuchs ERH, 2018. Science and research policy at the end of Moore’s law. Nat Electron, 1(1):14-21.

[18]Lau JH, 2022. Recent advances and trends in advanced packaging. IEEE Trans Compon Packag Manuf Technol, 12(2):228-252.

[19]Lee CY, Won CH, Jung S, et al., 2025. 3D integrated process and hybrid bonding of high bandwidth memory (HBM). Electron Mater Lett, 21(3):395-419.

[20]Leiserson CE, Thompson NC, Emer JS, et al., 2020. There’s plenty of room at the top: what will drive computer performance after Moore’s law? Science, 368(6495):eaam9744.

[21]Lv P, Liu QR, Wu JX, et al., 2018. New generation software-defined architecture. Sci Sin Inform, 48(3):315-328 (in Chinese).

[22]Ma XH, Wang Y, Wang YJ, et al., 2022. Survey on chiplets: interface, interconnect and integration methodology. CCF Trans High Perform Comput, 4(1):43-52.

[23]Miller DAB, 2017. Meshing optics with applications. Nat Photonics, 11(7):403-404.

[24]Mukkara A, Beckmann N, Abeydeera M, et al., 2018. Exploiting locality in graph analytics through hardware-accelerated traversal scheduling. 51st Annual IEEE/ACM Int Symp on Microarchitecture, p.1-14.

[25]Pal S, 2021. Scale-out Packageless Processing. PhD Thesis, University of California, Los Angeles, USA.

[26]Prashanth A, N V, 2024. An adaptive software defined network-on-chip (SD-NoC) for varying network resources in offering optimal service quality: survey. 1st Int Conf on Sustainability and Technological Advancements in Engineering Domain, p.226-231.

[27]Radamson HH, Zhu HL, Wu ZH, et al., 2020. State-of-the-art and future perspectives in advanced CMOS technology. Nanomaterials, 10(8):1555.

[28]Rudolph C, Hanisch A, Voigtländer M, et al., 2021. Enabling D2W/D2D hybrid bonding on manufacturing equipment based on simulated process parameters. IEEE 71st Electronic Components and Technology Conf, p.40-44.

[29]Salvador ID, Remberto SA, Brox M, et al., 2017. Software defined network controller: a neat solution administration for reconfigurable multi-core NoC. Int Conf on ReConFigurable Computing and FPGAs, p.1-4.

[30]Sandoval-Arechiga R, Vazquez-Avila JL, Parra-Michel R, et al., 2015. Shifting the network-on-chip paradigm towards a software defined network architecture. Int Conf on Computational Science and Computational Intelligence, p.869-870.

[31]Sandoval-Arechiga R, Ibarra-Delgado S, Flores-Troncoso J, 2017. A software defined interconnection architecture for systems on chip. Difu100ci@, Revista de difusión científica, ingeniería y tecnologías, 10(2):2-11.

[32]Shalf J, 2020. The future of computing beyond Moore’s law. Philos Trans A Math Phys Eng Sci, 378(2166):20190061.

[33]Sivaraman A, Kim C, Krishnamoorthy R, et al., 2011. DC.p4: programming the forwarding plane of a data-center switch. Proc 1st ACM SIGCOMM Symp on Software Defined Networking Research, p.1-8.

[34]Sivaraman A, Subramanian S, Alizadeh M, et al., 2016. Programmable packet scheduling at line rate. Proc ACM SIGCOMM Conf, p.44-57.

[35]Theis TN, Wong HSP, 2017. The end of Moore’s law: a new beginning for information technology. Comput Sci Eng, 19(2):41-50.

[36]Wu JX, Liu QR, Shen JL, et al., 2024. From SoC to SDSoW: a new paradigm for microelectronics development. Sci Sin Inform, 54(6):1350-1368 (in Chinese).

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Full Text:   <678>

CLC number: TP303

On-line Access: 2026-05-27

Received: 2025-09-30

Revision Accepted: 2026-03-13

Crosschecked: 2026-05-27

Cited: 0

Clicked: 850

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Ping LV

0009-0008-1608-6597

Qinrang LIU

0000-0002-9957-7365

Jiangxing WU

0000-0003-0255-0826

Jianliang SHEN

0009-0000-5647-043X

Mengke LIAN

0009-0007-4677-2566

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