Journal of Zhejiang University

Articles in Press: <EITEE>

ENGINEERING Information Technology & Electronic Engineering

ISSN 3069-8928 (print), ISSN 3069-8936 (online), CN 33-1439/TP

Accepted manuscript available online (unedited version)

CONTENTS

High-precision temperature prediction under atmospheric refractivity cor-rection using Kalman spatiotemporal data fusion

Ziru LI^1,^2,³, Zhaobin XU^1,^2,^3*, Tao ZHANG^1,^2,³, Xinbo YUAN^1,^2,³, Zhonghe JIN^1,^2,³

DOI: 10.1631/ENG.ITEE.2025.0005 Downloaded: 292 Clicked: 581 Cited: 0 Commented: 0(p.) <Full Text> <PPT > 284

Chinese summary <> FTHOE：一种面向晶圆级互连网络的哈密顿驱动容错路由算法

侯帅康¹，刘勤让²，张文博¹，吕平¹，李沛杰¹，郭威¹
¹信息工程大学，中国郑州市，450001
²复旦大学大数据研究院，中国上海市，200433
摘要：随着应用场景日益复杂，晶圆级系统对互连网络可靠性提出愈发严苛的要求。在不可避免的工艺制造缺陷和环境干扰下，晶圆级互连网络中节点和链路故障频发，使得容错能力成为提升系统整体可靠性关键因素。针对晶圆级互连网络中的芯片粒节点故障和链路故障，本文提出一种名为FTHOE的负载均衡无虚通道容错路由算法。该算法基于哈密顿路由策略和奇偶转向模型，通过利用当前节点的本地故障向量信息，动态调整输出端口选择优先级，从而在绕开故障区域时缩短迂回路径，并有效降低数据包陷入故障邻域的概率。同时，FTHOE在故障条件下保留了哈密顿路由的自适应特性，维持较高的最短路径多样性，进而增强网络负载均衡能力与整体通信性能。仿真结果表明，与现有容错路由算法相比，FTHOE显著降低了平均网络延迟并提高了吞吐量，在复杂故障场景下展现出鲁棒的容错能力和负载均衡性能。

关键词组：晶圆级系统；容错；哈密顿路径；奇偶转向模型；负载均衡

From software-defined interconnect to software-defined system-on-wafer: a computing architecture revolution in the post-Moore era

Ping LV¹, Qin-rang LIU², Jiangxing WU³, Jianliang SHEN¹, Mengke LIAN¹, Rui CAO¹, Shuai WEI¹, Zhichao LI¹,Peijie LI¹, Wei GUO¹, Wenjian ZHANG¹, Hong YU¹, Yan ZHAO¹

DOI: 10.1631/ENG.ITEE.2025.0063 Downloaded: 313 Clicked: 551 Cited: 0 Commented: 0(p.) <Full Text>

Unsupervised Single-Image High Dynamic Range Rendering via Multi-Exposure Priors

Han Wang¹, Bolun Zheng¹, Quan Chen², Qianyu Zhang¹, Tao Zhang¹, Jiyong Zhang¹, Xiang Tian³

DOI: 10.1631/ENG.ITEE.2025.0116 Downloaded: 72 Clicked: 107 Cited: 0 Commented: 0(p.) <Full Text>

MH-Raft: an efficient and low-latency consensus algorithm for distributed systems via MOEA/D and hybrid hierarchical clustering

Fei ZHAO, Guilong PENG, Tianyi ZANG

DOI: 10.1631/ENG.ITEE.2025.0043 Downloaded: 45 Clicked: 122 Cited: 0 Commented: 0(p.) <Full Text>

An approach to characterize the power system security region by integrating distributionally robust optimization and Transformer-based deep learning

Yuekai CHEN, Zhejing BAO^*, Miao YU

DOI: 10.1631/ENG.ITEE.2026.0024 Downloaded: 62 Clicked: 117 Cited: 0 Commented: 0(p.) <Full Text>

A hybrid redundancy and serialization fault-tolerant architecture for through-silicon via interconnects

Chenglong SUN^1,², Yanqing ZHOU^1,², Qi WANG^3*, Yan ZHANG^1,²

DOI: 10.1631/ENG.ITEE.2025.0156 Downloaded: 42 Clicked: 113 Cited: 0 Commented: 0(p.) <Full Text>