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CLC number: TP391.7

On-line Access: 2025-10-13

Received: 2024-07-21

Revision Accepted: 2025-03-25

Crosschecked: 2025-10-13

Cited: 0

Clicked: 598

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Jie YANG

https://orcid.org/0000-0001-7933-8220

Bin YAN

https://orcid.org/0000-0002-0393-9641

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Frontiers of Information Technology & Electronic Engineering  2025 Vol.26 No.9 P.1534-1550

http://doi.org/10.1631/FITEE.2400612


A review of automatic schematic generation techniques and their application to printed circuit boards


Author(s):  Jie YANG, Kai QIAO, Jian CHEN, Chen CHEN, Lixiang GUO, Bin YAN

Affiliation(s):  Information Engineering University, Zhengzhou 450000, China

Corresponding email(s):   evil126126@126.com, qiaokai1992@gmail.com, ybspace@hotmail.com

Key Words:  Automatic schematic generation, Layout, Routing, Printed circuit board, Reverse engineering, Automation


Jie YANG, Kai QIAO, Jian CHEN, Chen CHEN, Lixiang GUO, Bin YAN. A review of automatic schematic generation techniques and their application to printed circuit boards[J]. Frontiers of Information Technology & Electronic Engineering, 2025, 26(9): 1534-1550.

@article{title="A review of automatic schematic generation techniques and their application to printed circuit boards",
author="Jie YANG, Kai QIAO, Jian CHEN, Chen CHEN, Lixiang GUO, Bin YAN",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="26",
number="9",
pages="1534-1550",
year="2025",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2400612"
}

%0 Journal Article
%T A review of automatic schematic generation techniques and their application to printed circuit boards
%A Jie YANG
%A Kai QIAO
%A Jian CHEN
%A Chen CHEN
%A Lixiang GUO
%A Bin YAN
%J Frontiers of Information Technology & Electronic Engineering
%V 26
%N 9
%P 1534-1550
%@ 2095-9184
%D 2025
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2400612

TY - JOUR
T1 - A review of automatic schematic generation techniques and their application to printed circuit boards
A1 - Jie YANG
A1 - Kai QIAO
A1 - Jian CHEN
A1 - Chen CHEN
A1 - Lixiang GUO
A1 - Bin YAN
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 26
IS - 9
SP - 1534
EP - 1550
%@ 2095-9184
Y1 - 2025
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2400612


Abstract: 
The printed circuit board (PCB) stands as the cornerstone of electronic equipment, with its schematic holding paramount importance for system performance and reliability. In light of the pervasive use of electronic devices in society, concerns regarding maintenance, safety, backdoors, and other latent issues have garnered significant attention. automatic schematic generation (ASG), with its distinct capability for generating circuit schematics autonomously, not only plays a pivotal role in electronic design automation (EDA) but also aids in deciphering the fundamental principles of PCB equipment to effectively address these underlying issues. However, constrained by the increasingly sophisticated manufacturing processes of PCBs and the inherent legal and ethical controversies surrounding reverse engineering, the development of related technologies faces notable bottlenecks. To break through technical barriers and advance technological progress, this paper comprehensively combs through the existing ASG, offers in-depth description of the core algorithms of the technology—layout and routing, and for the application of the technology in PCB reverse engineering, analyzes in detail the current challenges and the faced problems. Around these challenges, feasible solutions are discussed in this paper, with the aims of promoting the research of automatic PCB schematic generation technology and contributing new strength to EDA and PCB reverse engineering automation.

自动原理图生成技术综述及其在印刷电路板中的应用

杨杰,乔凯,陈健,陈辰,郭利翔,闫镔
信息工程大学,中国郑州市,450000
摘要:印刷电路板(PCB)是电子设备的基石,其原理图对系统性能与可靠性具有至关重要的影响。随着电子设备在社会中的广泛应用,其维护、安全、后门以及其他潜在问题备受关注。自动原理图生成(ASG)凭借其自主生成电路原理图的独特能力,不仅在电子设计自动化(EDA)中扮演着举足轻重的角色,更能助力解析PCB设备的基本原理,从而有效应对这些深层问题。然而,受制于PCB日趋精密化的制造工艺以及逆向工程固有的法律和伦理争议,相关技术发展面临显著瓶颈。为突破技术壁垒,推动技术进步,本文系统梳理现有ASG技术,深入剖析其核心算法--布局与布线技术,并针对该技术在PCB逆向工程中的应用,详细分析当前面临的挑战和难题。围绕这些挑战,本文探讨了可行解决方案,旨在推动自动PCB原理图生成技术的研究,为EDA和PCB逆向工程自动化贡献新的力量。

关键词:自动原理图生成;布局;布线;印刷电路板;逆向工程;自动化

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

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