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CLC number: TN92; TN43

On-line Access: 2021-04-15

Received: 2020-09-28

Revision Accepted: 2021-01-06

Crosschecked: 2021-02-24

Cited: 0

Clicked: 1275

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Hongchen Chen

https://orcid.org/0000-0002-9980-381X

Quan Xue

https://orcid.org/0000-0002-4226-2127

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Frontiers of Information Technology & Electronic Engineering  2021 Vol.22 No.4 P.586-598

http://doi.org/10.1631/FITEE.2000510


A 9.8–30.1 GHz CMOS low-noise amplifier with a 3.2-dB noise figure using inductor- and transformer-based gm-boosting techniques


Author(s):  Hongchen Chen, Haoshen Zhu, Liang Wu, Wenquan Che, Quan Xue

Affiliation(s):  Guangdong Provincial Key Laboratory of Millimeter-Wave and Terahertz, School of Electronic and Information Engineering, South China University of Technology, Guangzhou 510641, China; more

Corresponding email(s):   hongdoublechen@gmail.com, zhuhs@scut.edu.cn, wuliang@cuhk.edu.cn, eewqche@scut.edu.cn, eeqxue@scut.edu.cn

Key Words:  CMOS, gm-boosting, Low-noise amplifier, Transformer, Common-gate


Hongchen Chen, Haoshen Zhu, Liang Wu, Wenquan Che, Quan Xue. A 9.8–30.1 GHz CMOS low-noise amplifier with a 3.2-dB noise figure using inductor- and transformer-based gm-boosting techniques[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(4): 586-598.

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Abstract: 
A 9.8–30.1 GHz CMOS low-noise amplifier (LNA) with a 3.2-dB minimum noise figure (NF) is presented. At the architecture level, a topology based on common-gate (CG) cascading with a common-source (CS) amplifier is proposed for simultaneous wideband input matching and relatively high gain. At the circuit level, multiple techniques are proposed to improve LNA performance. First, in the CG stage, loading effect is properly used instead of the conventional feedback technique, to enable simultaneous impedance and noise matching. Second, based on in-depth theoretical analysis, the inductor- and transformer-based gm-boosting techniques are employed for the CG and CS stages, respectively, to enhance the gain and reduce power consumption. Third, the floating-body method, which was originally proposed to lower NF in CS amplifiers, is adopted in the CG stage to further reduce NF. Fabricated in a 65-nm CMOS technology, the LNA chip occupies an area of only 0.2 mm2 and measures a maximum power gain of 10.9 dB with −3 dB bandwidth from 9.8 to 30.1 GHz. The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth. The LNA consumes 15.6 mW from a 1.2-V supply.

基于电感和变压器跨导提升技术、噪声系数为3.2 dB、带宽为9.8-30.1 GHz的CMOS低噪声放大器

陈宏尘1,朱浩慎1,吴亮2,车文荃1,薛泉1
1华南理工大学电子与信息学院毫米波与太赫兹广东省重点实验室,中国广州市,510641
2香港中文大学(深圳)理工学院,中国深圳市,518172
概要:随着第五代移动通信系统(5G)的到来,毫米波收发系统预期将陆续在世界范围内大规模商用部署。对于接收机来说,最关键的指标是要保持较高信噪比。因此,位于接收机前端的第一个有源模块--低噪声放大器--起着非常关键的作用。但是,当频率上升到毫米波段时,由于寄生效应影响变大,高性能的宽带低噪声放大器设计面临着诸多挑战。本文通过基于电感和变压器的跨导提升技术,研制一款宽带的高性能毫米波低噪声放大器。使用台积电(TSMC)65 nm CMOS工艺流片并测试,这款低噪声放大器最低噪声系数仅为3.2 dB,带宽高达20.3 GHz,适用于5G毫米波收发系统。
利用共栅放大器(M1)和共源放大器(M2)级联构成完整的低噪声放大器。第一级选择共栅级是因为共栅放大器的输入阻抗低,易于实现宽带的输入匹配。但是,由于单纯的一级放大器增益不够,所以级联一个共源级作为第二级放大器提高增益。在低噪声放大器中,较高的增益通常需要更大功耗来实现,因此增益和功耗在实际设计中需要折中。但是,通过引入跨导提升技术,可以使得等效跨导Gm等于(1+A)gm,其中A是提升因子,gm是晶体管固有的跨导。如此,在同样功耗(gm)下,引入跨导提升技术可取得更高增益(Gm);反之,对于相同增益(Gm),引入跨导提升技术后只需要更小功耗(gm)。然而,传统的跨导提升方法,即通过有源反馈实现,会引入大量噪声。与传统方法不同,本文提出利用电感提升跨导和变压器提升跨导相结合的方式大幅提升第一级和第二级放大器的跨导。首先通过在第一级放大器(共栅级)加入栅极电感Lg,使Lg与晶体管M1的寄生电容在高频处谐振,从而提升M1的等效跨导。其次,针对第二级放大器(共源级),通过引入变压器TR1,使M2的栅极和源级同时输入反相信号,从而提升M2的等效跨导。通过仿真实验,可以看到引入电感后提升了第一级放大器的等效跨导。在第二级放大器引入变压器后等效跨导随耦合系数变化,可以看到,当耦合系数为0时,等效跨导最低,随着耦合系数增大,等效跨导提升。
本文提出的宽带毫米波低噪声放大器经台积电65纳米CMOS工艺流片加工。去除测试PAD后的芯片面积仅为0.1μm2。该低噪声放大器采用在片测试方法测试。其中,S参数由德国R&S公司生成的ZVA67矢量网络分析仪测试。噪声系数由带有噪声系数测试选件K30的FSW67频谱分析仪和Noisecom公司的噪声源NC346V测试。
测试结果表明,低噪声放大器最大增益为10.9 dB,3 dB带宽从9.8 GHz到30.1 GHz,高达20.3 GHz,并且输入匹配良好。另外,噪声系数最低仅为3.2 dB,且在整个3 dB带宽内低于5.7 dB。此外,整体功耗仅为15.6 mW。
由此可见,由于采用了基于电感和变压器的跨导提升技术,该毫米波低噪声放大器在带宽、增益和噪声系数方面表现优异,适用于5G毫米波收发系统。

关键词:CMOS;跨导提升技术;低噪声放大器;变压器;共栅级

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

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