Full Text:   <2335>

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CLC number: TN79

On-line Access: 2023-03-25

Received: 2022-08-28

Revision Accepted: 2022-11-22

Crosschecked: 2023-03-25

Cited: 0

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Citations:  Bibtex RefMan EndNote GB/T7714


Mohammad GHOLAMI


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Frontiers of Information Technology & Electronic Engineering  2023 Vol.24 No.3 P.457-469


Low-power, high-speed, and area-efficient sequential circuits by quantum-dot cellular automata: T-latch and counter study

Author(s):  Mohammad GHOLAMI, Zaman AMIRZADEH

Affiliation(s):  Department of Electrical Engineering, Faculty of Engineering and Technology, University of Mazandaran, Babolsar 4741613534, Iran; more

Corresponding email(s):   m.gholami@umz.ac.ir

Key Words:  Quantum-dot cellular automata (QCA), Quantum-dot, T-latch, T-flip-flop, Counter, Selective counter, QCADesigner, QCAPro

Mohammad GHOLAMI, Zaman AMIRZADEH. Low-power, high-speed, and area-efficient sequential circuits by quantum-dot cellular automata: T-latch and counter study[J]. Frontiers of Information Technology & Electronic Engineering, 2023, 24(3): 457-469.

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%A Mohammad GHOLAMI
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%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2200361

T1 - Low-power, high-speed, and area-efficient sequential circuits by quantum-dot cellular automata: T-latch and counter study
A1 - Mohammad GHOLAMI
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 24
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quantum-dot cellular automata (QCA)%29&ck%5B%5D=abstract&ck%5B%5D=keyword'>quantum-dot cellular automata (QCA) is a new nanotechnology for the implementation of nano-sized digital circuits. This nanotechnology is remarkable in terms of speed, area, and power consumption compared to complementary metal-oxide-semiconductor (CMOS) technology and can significantly improve the design of various logic circuits. We propose a new method for implementing a t-latch in QCA technology in this paper. The proposed method uses the intrinsic features of QCA in timing and clock phases, and therefore, the proposed cell structure is less occupied and less power-consuming than existing implementation methods. In the proposed t-latch, compared to previous best designs, reductions of 6.45% in area occupation and 44.49% in power consumption were achieved. In addition, for the first time, a reset-based t-latch and a t-latch with set and reset capabilities are designed. Using the proposed t-latch, a new 3-bit counter is developed which reduces 2.14% cell numbers compared to the best of previous designs. Moreover, based on the 3-bit counter, a 4-bit counter is designed, which reduces 0.51% cell numbers and 4.16% cross-section area compared to previous designs. In addition, two selective counters are introduced to count from 0 to 5 and from 2 to 5. Simulations were performed using QCADesigner and QCAPro tools in coherence vector engine mode. The proposed circuits are compared with related designs in terms of delay, cell numbers, area, and leakage power.




Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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