Full Text:   <632>

Summary:  <221>

CLC number: TN402

On-line Access: 2024-05-06

Received: 2023-07-05

Revision Accepted: 2024-05-06

Crosschecked: 2023-12-17

Cited: 0

Clicked: 684

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Zhengzhou CAO

https://orcid.org/0009-0004-7988-1003

Guozhu LIU

https://orcid.org/0000-0003-4358-3309

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Frontiers of Information Technology & Electronic Engineering  2024 Vol.25 No.4 P.485-499

http://doi.org/10.1631/FITEE.2300454


Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH


Author(s):  Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, Yueer SHAN, Yuting XU

Affiliation(s):  No. 58 Research Institute, China Electronics Technology Group Corporation, Wuxi 214035, China

Corresponding email(s):   caozhengzhou@163.com

Key Words:  Field programmable gate array (FPGA), Programmable logic element (PLE), Boolean logic operation, Look-up table, Sense-Switch pFLASH, Threshold voltage


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Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, Yueer SHAN, Yuting XU. Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH[J]. Frontiers of Information Technology & Electronic Engineering, 2024, 25(4): 485-499.

@article{title="Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH",
author="Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, Yueer SHAN, Yuting XU",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="25",
number="4",
pages="485-499",
year="2024",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2300454"
}

%0 Journal Article
%T Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH
%A Zhengzhou CAO
%A Guozhu LIU
%A Yanfei ZHANG
%A Yueer SHAN
%A Yuting XU
%J Frontiers of Information Technology & Electronic Engineering
%V 25
%N 4
%P 485-499
%@ 2095-9184
%D 2024
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2300454

TY - JOUR
T1 - Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH
A1 - Zhengzhou CAO
A1 - Guozhu LIU
A1 - Yanfei ZHANG
A1 - Yueer SHAN
A1 - Yuting XU
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 25
IS - 4
SP - 485
EP - 499
%@ 2095-9184
Y1 - 2024
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2300454


Abstract: 
This paper proposes a kind of programmable logic element (PLE) based on sense-Switch pFLASH technology. By programming sense-Switch pFLASH, all three-bit look-up table (LUT3) functions, partial four-bit look-up table (LUT4) functions, latch functions, and d flip flop (DFF) with enable and reset functions can be realized. Because PLE uses a choice of operational logic (COOL) approach for the operation of logic functions, it allows any logic circuit to be implemented at any ratio of combinatorial logic to register. This intrinsic property makes it close to the basic application specific integrated circuit (ASIC) cell in terms of fine granularity, thus allowing ASIC-like cell-based mappers to apply all their optimization potential. By measuring sense-Switch pFLASH and PLE circuits, the results show that the “on” state driving current of the sense-Switch pFLASH is about 245.52 μA, and that the “off” state leakage current is about 0.1 pA. The programmable function of PLE works normally. The delay of the typical combinatorial logic operation AND3 is 0.69 ns, and the delay of the sequential logic operation DFF is 0.65 ns, both of which meet the requirements of the design technical index.

基于Sense-Switch型pFLASH的FPGA可编程逻辑单元的

设计与验证
曹正州,刘国柱,张艳飞,单悦尔,徐玉婷
中国电子科技集团公司第58研究所,中国无锡市,214035
摘要:本文提出一种基于Sense-Switch型pFLASH技术的可编程逻辑单元(PLE)。通过对Sense-Switch型pFLASH进行编程,实现所有的三位查找表(LUT3)功能、部分LUT4功能、锁存器功能以及带使能和复位的DFF功能。因为PLE使用了一种选择运算逻辑(COOL)的方法来运算逻辑函数,它允许使用任意组合逻辑和寄存器的比例来实现任意逻辑电路。这一本质特性使其在精细粒度方面接近于基本的ASIC单元,从而允许类似ASIC的基于单元的映射器应用其所有的优化潜力。对Sense-Switch型pFLASH和PLE电路的实测结果表明Sense-Switch型pFLASH的"开态"驱动电流约为245.52 µA、"关态"漏电流约为0.1 pA;PLE的可编程功能正常工作;典型的组合逻辑运算AND3的延迟为0.69 ns、时序逻辑DFF的延迟为0.65 ns,均满足设计技术指标的要求。

关键词:现场可编程门阵列;可编程逻辑单元;布尔逻辑运算;查找表;Sense-Switch型pFLASH;阈值电压

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

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