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Journal of Zhejiang University SCIENCE A 2009 Vol.10 No.7 P.1067~1074

10.1631/jzus.A0820566


New method for high performance multiply-accumulator design


Author(s):  Bing-jie XIA, Peng LIU, Qing-dong YAO

Affiliation(s):  Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   icysummer@zju.edu.cn, liupeng@isee.zju.edu.cn

Key Words:  Multiply-accumulator (MAC), Pipeline, Compressor, Partial product reduction tree (PPRT), Split structure


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Bing-jie XIA, Peng LIU, Qing-dong YAO. New method for high performance multiply-accumulator design[J]. Journal of Zhejiang University Science A, 2009, 10(7): 1067~1074.

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Abstract: 
This study presents a new method of 4-pipelined high-performance split multiply-accumulator (MAC) architecture, which is capable of supporting multiple precisions developed for media processors. To speed up the design further, a novel partial product compression circuit based on interleaved adders and a modified hybrid partial product reduction tree (PPRT) scheme are proposed. The MAC can perform 1-way 32-bit, 4-way 16-bit signed/unsigned multiply or multiply-accumulate operations and 2-way parallel multiply add (PMADD) operations at a high frequency of 1.25 GHz under worst-case conditions and 1.67 GHz under typical-case conditions, respectively. Compared with the MAC in 32-bit microprocessor without interlocked piped stages (MIPS), the proposed design shows a great advantage in speed. Moreover, an improvement of up to 32% in throughput is achieved. The MAC design has been fabricated with Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS standard cell technology and has passed a functional test.

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