| index | Title |
| 1 | Layer-layout-based heuristics for loading homogeneous items into a single container Author(s):WANG Zhou-jing, LI Kevin W. Clicked:7545 Download:3914 Cited:2 <Full Text> Journal of Zhejiang University Science A 2007 Vol.8 No.12 P.1944-1952 DOI:10.1631/jzus.2007.A1944 |
| 2 | HAPE3D—a new constructive algorithm for the 3D irregular packing problem Author(s):Xiao Liu, Jia-min Liu, An-xi Cao, ... Clicked:11367 Download:5523 Cited:0 <Full Text> <PPT> 3236 Frontiers of Information Technology & Electronic Engineering 2015 Vol.16 No.5 P.380-390 DOI:10.1631/FITEE.1400421 |
| 3 | Multi-objective layout optimization of a satellite module using the Wang-Landau sampling method with local ... Author(s):Jing-fa Liu, Liang Hao, Gang Li, Y... Clicked:10110 Download:4392 Cited:4 <Full Text> <PPT> 2703 Frontiers of Information Technology & Electronic Engineering 2016 Vol.17 No.6 P.527-542 DOI:10.1631/FITEE.1500292 |
| 4 | Layout design and application of 4D-printing bio-inspired structures with programmable actuators Author(s):Siyuan Zeng, Yixiong Feng, Yicong ... Clicked:2667 Download:3424 Cited:0 <Full Text> Journal of Zhejiang University Science 2004 Vol.5 No.1 P.189-200 DOI:10.1007/s42242-021-00146-3 |
| 5 | Iris: a multi-constraint graphic layout generation system Author(s):Liuqing CHEN, Qianzhi JING, Yixin ... Clicked:3669 Download:4039 Cited:0 <Full Text> <PPT> 862 Frontiers of Information Technology & Electronic Engineering 2024 Vol.25 No.7 P.968-987 DOI:10.1631/FITEE.2300312 |
| 6 | WSC optimizer: an optimization tool for wafer-scale chip architecture exploration Author(s):Wenbo ZHANG, Bo DING, Shuai WEI, Q... Clicked:132 Download:37 Cited:0 <Full Text> <PPT> 67 Journal of Zhejiang University Science 2026 Vol.27 No.4 P.1-16 DOI:10.1631/ENG.ITEE.2025.0008 |