ENGINEERING Information Technology & Electronic Engineering 

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From software-defined interconnect to software-defined system-on-wafer: a computing architecture revolution in the post-Moore era


Author(s):  Ping LV1, Qin-rang LIU2, Jiangxing WU3, Jianliang SHEN1, Mengke LIAN1, Rui CAO1, Shuai WEI1, Zhichao LI1, Peijie LI1, Wei GUO1, Wenjian ZHANG1, Hong YU1, Yan ZHAO1

Affiliation(s):  1Information Engineering University, Zhengzhou 450001, China 2Institute of Big Data, Fudan University, Shanghai 200433, China 3National Digital Switching System Engineering & Technology Research Center, Zhengzhou 450002, China

Corresponding email(s):  Qinrang LIU, qinrangliu@sina.com

Key Words:  Software-defined interconnect; Software-defined system-on-wafer; Wafer-level integration; Emergent intelligence;Heterogeneous computing


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Ping LV1, Qin-rang LIU2, Jiangxing WU3, Jianliang SHEN1, Mengke LIAN1, Rui CAO1, Shuai WEI1, Zhichao LI1,Peijie LI1, Wei GUO1, Wenjian ZHANG1, Hong YU1, Yan ZHAO1. From software-defined interconnect to software-defined system-on-wafer: a computing architecture revolution in the post-Moore era[J]. Journal of Zhejiang University Science ,in press.Frontiers of Information Technology & Electronic Engineering,in press.https://doi.org/10.1631/ENG.ITEE.2025.0063

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journal="Journal of Zhejiang University Science ",
year="in press",
publisher="Zhejiang University Press & Springer",
doi="https://doi.org/10.1631/ENG.ITEE.2025.0063"
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%A Hong YU1
%A Yan ZHAO1
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A1 - Zhichao LI1
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Abstract: As Moore's Law approaches its fundamental physical and economic limits, the semiconductor industry faces unprecedented challenges in maintaining performance growth. This study presents the revolutionary evolution from software-defined interconnect (SDI) to software-defined system-on-wafer (SDSoW), a paradigm-shifting architectural approach that transcends traditional scaling constraints through wafer-level heterogeneous integration. Our proposed SDSoW enables dynamic reconfiguration of thousands of computing chiplets across an entire wafer, achieving superlinear performance scaling and significantly improving energy efficiency. We established a comprehensive theoretical framework with mathematical models covering key aspects, such as interconnect flexibility and integration scaling, and proposed an application-driven dynamic architecture reconfiguration (ADR) paradigm that optimizes wafer-scale resources in real time and may foster emergent intelligence in large, heterogeneous systems. Simulation results (128-1024 nodes) demonstrate that SDSoW outperforms conventional multi-chip systems, delivering 3.5× higher throughput, 80% lower latency, and 2.5× better energy efficiency. As a paradigm shift comparable to the invention of integrated circuits (ICs), it provides a viable pathway beyond Moore's Law through innovative architectural design rather than process scaling.

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On-line Access: 2026-04-07

Received: 2025-09-30

Revision Accepted: 2026-03-13

Crosschecked: 0000-00-00

Cited: 0

Clicked: 422

Citations:  Bibtex RefMan EndNote GB/T7714

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