
CLC number: TP183; TN6
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2021-05-08
Cited: 0
Clicked: 8795
Citations: Bibtex RefMan EndNote GB/T7714
https://orcid.org/0000-0003-2975-4976
Yifei Pu, Bo Yu, Qiuyan He, Xiao Yuan. Fractional-order memristive neural synaptic weighting achieved by pulse-based fracmemristor bridge circuit[J]. Frontiers of Information Technology & Electronic Engineering,in press.https://doi.org/10.1631/FITEE.2000085 @article{title="Fractional-order memristive neural synaptic weighting achieved by pulse-based fracmemristor bridge circuit", %0 Journal Article TY - JOUR
基于脉冲分忆抗桥电路的分数阶记忆性神经突触加权1四川大学计算机学院(软件学院),中国成都市,610065 2成都师范学院物理与工程技术学院,中国成都市,611130 3四川大学电子信息学院,中国成都市,610065 摘要:提出一种新颖的分数阶记忆性神经突触加权电路。与以往大多数整数阶神经突触加权电路不同,该分数阶记忆性神经突触加权电路具有许多重要优点。由于忆阻的概念已从经典的整数阶忆阻推广到分数阶忆阻(分忆抗),分忆抗能否实现分数阶记忆性突触成为一个具有挑战性的理论问题。本文研究利用脉冲分忆抗桥电路实现的分数阶记忆性神经突触加权电路的特点。首先,利用基于脉冲的分忆抗桥电路设计分数阶记忆性神经突触加权电路结构。其次,从数学上证明分数阶记忆性神经突触加权电路的分数阶学习能力。最后,通过实验研究分数阶记忆性神经突触加权电路的电特性。分数阶记忆性神经突触加权电路在解释学习和记忆基础的细胞机制方面具有很强的能力,优于传统的整数阶神经突触加权电路,是该电路的主要优势。 关键词组: Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article
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