Abstract: AutoDock Vina (Vina) is a widely adopted molecular docking tool, often regarded as a standard or used as a baseline in numerous studies. However, its computational process is highly time-consuming. The pioneering FPGA-based accelerator of Vina, known as Vina-FPGA, ofers a high energy-efficiency approach to speedup the docking process. However, the computation modules in the Vina-FPGA design are not efficiently utilized. This is due to Vina exhibiting irregular behaviors in the form of nested loops with changing upper bounds and difering control flows. Fortunately, Vina employs the Monte Carlo iterative search method, which requires independent computations for diferent random initial inputs (tasks) . This characteristic provides an opportunity to implement further parallel computation designs. To this end, this paper proposes Vina-FPGA2, an inter-module pipeline design for further accelerating Vina-FPGA. First, we utilized task independence by sequentially filling tasks into computation modules. Then, we implemented an inter-module pipeline parallel design by the Tag Checker module and architectural modifications, named Vina-FPGA2-Baseline. Next, to achieve resource-efficient hardware implementation, we described it as an optimization problem and developed a reinforcement learning-based solver. Targeting the Xilinx UltraScale XCKU060 platform, this solver yields a more efficient implementation, named Vina-FPGA2-Enhanced. Finally, experiments show that Vina-FPGA2-Enhanced achieves an average 12.6 × performance improvement over the CPU and a 3.3 × improvement over Vina-FPGA. Compared to Vina-GPU, Vina-FPGA2 achieves a 7.2 × enhancement in energy efficiency.