Full Text:
<2423>
Summary: 
<1692>
CLC number: TN79
On-line Access: 2016-08-31
Received: 2015-09-20
Revision Accepted: 2016-02-16
Crosschecked: 2016-08-08
Cited: 0
Clicked: 6223
A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm
| ||||||||||||||
Xing-ru Peng, Wei Zhang, Yan-yan Liu. A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(9): 954-961.
@article{title="A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm",
author="Xing-ru Peng, Wei Zhang, Yan-yan Liu",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="17",
number="9",
pages="954-961",
year="2016",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1500303"
}
%0 Journal Article
%T A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm
%A Xing-ru Peng
%A Wei Zhang
%A Yan-yan Liu
%J Frontiers of Information Technology & Electronic Engineering
%V 17
%N 9
%P 954-961
%@ 2095-9184
%D 2016
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1500303
TY - JOUR
T1 - A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm
A1 - Xing-ru Peng
A1 - Wei Zhang
A1 - Yan-yan Liu
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 17
IS - 9
SP - 954
EP - 961
%@ 2095-9184
Y1 - 2016
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.1500303
Abstract: We propose a pipelined Reed-Solomon (RS) decoder for an ultra-wideband system using a modified step-by-step algorithm. To reduce the complexity, the modified step-by-step algorithm merges two cases of the original algorithm. The pipelined structure allows the decoder to work at high rates with minimum delay. Consequently, for RS(23,17) codes, the proposed architecture requires 42.5% and 24.4% less area compared with a modified Euclidean architecture and a pipelined degree-computationless modified Euclidean architecture, respectively. The area of the proposed decoder is 11.3% less than that of the previous step-by-step decoder with a lower critical path delay.
This paper proposed a pipelined Reed-Solomon decoder based on a modified step-by-step algorithm. The area of the proposed decoder was shown less than the existing results. The paper is easy to follow.
[1]Baek, J.H., Sunwoo, M.H., 2006. New degree computationless modified Euclid algorithm and architecture for Reed-Solomon decoder. IEEE Trans. VLSI Syst., 14(8):915-920.
[2]Batra, A., Balakrishnan, J., Dabak, A., et al., 2004. Multi-band OFDM Physical Layer Proposal for IEEE 802.15 Task Group 3a. IEEE P802.15-03/268r2.
[3]Berlekamp, E.R., 1968. Algebraic Coding Theory. McGraw-Hill, New York.
[4]Chen, T.C., Tasi, M.H., 2007. Hardware implementation of a high-speed (32, 24, 4) RS decoder. Chung Hua J. Sci. Eng., 5(4):21-27.
[5]Chen, T.C., Wei, C.H., Wei, S.W., 2000. Step-by-step decoding algorithm for Reed-Solomon codes. IEE Proc. Commun., 147(1):8-12.
[6]Chen, T.C., Wei, C.H., Wei, S.W., 2003. A pipeline structure for high-speed step-by-step RS decoding. IEICE Trans. Commun., E86-B(2):847-849.
[7]Das, A.S., Das, S., Bhaumik, J., 2013. Design of RS(255,251) encoder and decoder in FPGA. Int. J. Soft Comput. Eng., 2(6):391-394.
[8]García-Herrero, F., Valls, J., Meher, P.K., 2011. High-speed RS(255, 239) decoder based on LCC decoding. Circ. Syst. Signal Process., 30(6):1643-1669.
[9]Guo, W., Gai, W., 2014. Area-efficient recursive degree computationless modified Euclid’s architecture for Reed-Solomon decoder. Proc. IEEE Int. Conf. on Electron Devices and Solid-State Circuits, p.1-2.
[10]Lee, H., 2003. High-speed VLSI architecture for parallel Reed-Solomon decoder. IEEE Trans. VLSI Syst., 11(2):288-294.
[11]Lee, S., Lee, H., 2008. A high-speed pipelined degree-computationless modified Euclidean algorithm architecture for Reed-Solomon decoders. IEICE Trans. Fundament. Electron. Commun. Comput. Sci., E91-A(3):830-835.
[12]Liu, X., Lu, C., Cheng, T.H., et al., 2007. A simplified step-by-step decoding algorithm for parallel decoding of Reed-Solomon codes. IEEE Trans. Commun., 55(6):1103-1109.
[13]Massey, J., 1965. Step-by-step decoding of the Bose-Chaudhuri-Hocquenghem codes. IEEE Trans. Inform. Theory, 11(4):580-585.
[14]Sarwate, D.V., Shanbhag, N.R., 2001. High-speed architectures for Reed-Solomon decoders. IEEE Trans. VLSI Syst., 9(5):641-655.
[15]Wu, Y., 2015. New scalable decoder architectures for Reed-Solomon codes. IEEE Trans. Commun., 63(8):2741-2761.
[16]Zhang, X., Zhu, J., 2010. High-throughput interpolation architecture for algebraic soft-decision Reed-Solomon decoding. IEEE Trans. Circ. Syst. I, 57(3):581-591.
[17]Zhu, J., Zhang, X., Wang, Z., 2009. Backward interpolation architecture for algebraic soft-decision Reed-Solomon decoding. IEEE Trans. VLSI Syst., 17(11):1602-1615.
ORCID: 
Open peer comments: Debate/Discuss/Question/Opinion
<1>