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CLC number: TN47

On-line Access: 2017-12-04

Received: 2016-11-21

Revision Accepted: 2016-12-20

Crosschecked: 2017-10-31

Cited: 0

Clicked: 1957

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Mao-qun Yao

http://orcid.org/0000-0001-6484-4972

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Frontiers of Information Technology & Electronic Engineering  2017 Vol.18 No.10 P.1654-1664

http://doi.org/10.1631/FITEE.1601730


Function synthesis algorithm based on RTD-based three-variable universal logic gates


Author(s):  Mao-qun Yao, Kai Yang, Ji-zhong Shen, Cong-yuan Xu

Affiliation(s):  Hangzhou Institute of Service Engineering, Hangzhou Normal University, Hangzhou 310036, China; more

Corresponding email(s):   yaomaoqun@163.com

Key Words:  Resonant tunneling device (RTD), Disjunctive decomposition algorithm, Universal logic gate, Truth value matrix, Function synthesis algorithm


Mao-qun Yao, Kai Yang, Ji-zhong Shen, Cong-yuan Xu. Function synthesis algorithm based on RTD-based three-variable universal logic gates[J]. Frontiers of Information Technology & Electronic Engineering, 2017, 18(10): 1654-1664.

@article{title="Function synthesis algorithm based on RTD-based three-variable universal logic gates",
author="Mao-qun Yao, Kai Yang, Ji-zhong Shen, Cong-yuan Xu",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="18",
number="10",
pages="1654-1664",
year="2017",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1601730"
}

%0 Journal Article
%T Function synthesis algorithm based on RTD-based three-variable universal logic gates
%A Mao-qun Yao
%A Kai Yang
%A Ji-zhong Shen
%A Cong-yuan Xu
%J Frontiers of Information Technology & Electronic Engineering
%V 18
%N 10
%P 1654-1664
%@ 2095-9184
%D 2017
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1601730

TY - JOUR
T1 - Function synthesis algorithm based on RTD-based three-variable universal logic gates
A1 - Mao-qun Yao
A1 - Kai Yang
A1 - Ji-zhong Shen
A1 - Cong-yuan Xu
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 18
IS - 10
SP - 1654
EP - 1664
%@ 2095-9184
Y1 - 2017
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.1601730


Abstract: 
Compared with complementary metal–oxide semiconductor (), the resonant tunneling device (RTD) has better performances; it is the most promising candidate for next-generation integrated circuit devices. The universal logic gate is an important unit circuit because of its powerful logic function, but there are few function synthesis algorithms that can implement an n-variable logical function by RTD-based universal logic gates. In this paper, we propose a new concept, i.e., the truth value matrix. With it a novel disjunctive decomposition algorithm can be used to decompose an arbitrary n-variable logical function into three-variable subset functions. On this basis, a novel function synthesis algorithm is proposed, which can implement arbitrary n-variable logical functions by RTD-based universal threshold logic gates (UTLGs), RTD-based three-variable XOR gates (XOR3s), and RTD-based three-variable universal logic gate (ULG3s). When this proposed function synthesis algorithm is used to implement an n-variable logical function, if the function is a directly disjunctive decomposition one, the circuit structure will be very simple, and if the function is a non-directly disjunctive decomposition one, the circuit structure will be simpler than when using only UTLGs or ULG3s. The proposed function synthesis algorithm is straightforward to program, and with this algorithm it is convenient to implement an arbitrary n-variable logical function by RTD-based universal logic gates.

基于RTD三变量通用逻辑门的函数综合算法

概要:共振隧穿器件(resonant tunneling device, RTD)比传统电子器件CMOS具有更优秀的性能,极有可能成为下一代集成电路的电子器件。通用逻辑门因其强大的逻辑功能,成为数字电路的重要单元电路,而目前基于RTD通用逻辑门实现n变量逻辑函数的综合算法还很缺乏。本文基于RTD通用逻辑门,提出实现任意n变量逻辑函数的综合算法。首先,提出真值矩阵的概念,并提出一种运用真值矩阵将任意n变量逻辑函数分解成3变量子集函数的非相交分解算法;在上述工作基础上,提出用基于RTD通用阈值逻辑门(universal threshold logic gates, UTLG)、基于RTD三变量异或门XOR3和基于RTD三变量通用逻辑门ULG3实现n变量逻辑函数的综合算法。当n变量逻辑函数为可直接非相交分解函数时,用所提出算法实现的电路十分简单;当n变量逻辑函数为不可直接非相交分解函数时,用所提算法实现的电路比用单一UTLG门或ULG3门实现n变量逻辑函数的电路简单。提出的综合算法规范、可程序化,可方便地用于设计基于RTD通用逻辑门的任意n变量逻辑函数电路。

关键词:共振隧穿器件(RTD);非相交分解算法;通用逻辑门;真值矩阵;函数综合算法

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