CLC number: TN43
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2023-05-06
Cited: 0
Clicked: 2264
Citations: Bibtex RefMan EndNote GB/T7714
Ayoub SADEGHI, Razieh GHASEMI, Hossein GHASEMIAN, Nabiollah SHIRI. Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits[J]. Frontiers of Information Technology & Electronic Engineering, 2023, 24(4): 599-616.
@article{title="Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits",
author="Ayoub SADEGHI, Razieh GHASEMI, Hossein GHASEMIAN, Nabiollah SHIRI",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="24",
number="4",
pages="599-616",
year="2023",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2200077"
}
%0 Journal Article
%T Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits
%A Ayoub SADEGHI
%A Razieh GHASEMI
%A Hossein GHASEMIAN
%A Nabiollah SHIRI
%J Frontiers of Information Technology & Electronic Engineering
%V 24
%N 4
%P 599-616
%@ 2095-9184
%D 2023
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2200077
TY - JOUR
T1 - Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits
A1 - Ayoub SADEGHI
A1 - Razieh GHASEMI
A1 - Hossein GHASEMIAN
A1 - Nabiollah SHIRI
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 24
IS - 4
SP - 599
EP - 616
%@ 2095-9184
Y1 - 2023
PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.2200077
Abstract: Carbon nanotube field-effect transistors (CNTFETs) are reliable alternatives for conventional transistors, especially for use in approximate computing (AC) based error-resilient digital circuits. In this paper, CNTFET technology and the gate diffusion input (GDI) technique are merged, and three new AC-based full adders (FAs) are presented with 6, 6, and 8 transistors, separately. The nondominated sorting based genetic algorithm II (NSGA-II) is used to attain the optimal performance of the proposed cells by considering the number of tubes and chirality vectors as its variables. The results confirm the circuits’ improvement by about 50% in terms of power-delay-product (PDP) at the cost of area occupation. The Monte Carlo method (MCM) and 32-nm CNTFET technology are used to evaluate the lithographic variations and the stability of the proposed circuits during the fabrication process, in which the higher stability of the proposed circuits compared to those in the literature is observed. The dynamic threshold (DT) technique in the transistors of the proposed circuits amends the possible voltage drop at the outputs. Circuitry performance and error metrics of the proposed circuits nominate them for the least significant bit (LSB) parts of more complex arithmetic circuits such as multipliers.
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