Abstract: This paper proposes a kind of programmable logic element (PLE) based on Sense-Switch pFLASH technology. By programming Sense-Switch pFLASH, all three-bit look-up table (LUT3) functions, partial four-bit look-up table (LUT4) functions, latch functions, and d flip flop (DFF) with enable and reset functions can be realized. Because PLE uses a choice of operational logic (COOL) approach for the operation of logic functions, it allows any logic circuit to be implemented at any ratio of combinatorial logic to register. This intrinsic property makes it close to the basic application specific integrated circuit (ASIC) cell in terms of fine granularity, thus allowing ASIC-like cell-based mappers to apply all their optimization potential. By measuring Sense-Switch pFLASH and PLE circuits, the results show that the “on” state driving current of the Sense-Switch pFLASH is about 245.52 μA, and that the “off” state leakage current is about 0.1 pA. The programmable function of PLE works normally. The delay of the typical combinatorial logic operation AND3 is 0.69 ns, and the delay of the sequential logic operation DFF is 0.65 ns, both of which meet the requirements of the design technical index.

基于Sense-Switch型pFLASH的FPGA可编程逻辑单元的

[1]Anjaneyulu O, Reddy CVK, 2023. A novel design of full adder cell for VLSI applications. Int J Electron, 110(4):670-685.

[2]Cai YM, Huang R, 2014. Method for Inhibiting Programming Disturbance of Flash Memory. US Patent20140017870.

[3]Cao ZZ, Shan YE, Zhang YF, et al., 2021. A Configuration Method of Flash-based FPGA with Multistep Control. China Patent CN202111582283.1(in Chinese).

[4]Cao ZZ, Liu GZ, Shan YE, et al., 2022a. A configuration circuit design for Flash-based FPGA. Microelectr Comput, 39(11):118-128(in Chinese).

[5]Cao ZZ, Liu GZ, Shan YE, et al., 2022b. A step configuration method for Flash-based FPGA. Microelectr Comput, 39(12):115-124(in Chinese).

[6]Cao ZZ, Shan YE, Zhang YF, 2023. Programming and disturb inhibit technology of Flash-based FPGA. Semicond Technol, 48(7):624-631(in Chinese).

[7]Chan VH, Liu DKY, 1999. An enhanced erase mechanism during channel Fowler‍–‍Nordheim tunneling in Flash EPROM memory devices. IEEE Electron Dev Lett, 20(3):140-142.

[8]Chou YL, Wang TH, Cheng CC, et al., 2021. Investigation of Vth distribution tails of ground-select-line cells and edge dummy cells in a 3-D NAND Flash memory. IEEE Trans Electron Dev, 68(5):2260-2264.

[9]Desnoyers P, Kandiraju G, 2016. INFLOW 2015: the Third Workshop on Interactions of NVM/FLash with Operating Systems and Workloads. ACM SIGOPS Oper Syst Rev, 49(2):17.

[10]Eddla A, Pappu VYJ, 2022. Low area and power-efficient FPGA implementation of improved AM-CSA-IIR filter design for the DSP application. Int J Electr Electron Eng Telecommun, 11(4):294-303.

[11]Jiang Y, He CY, Cao ZZ, et al., 2023. Current read out circuit for Flash-based FPGA. Electron Pack, 23(4):040301(in Chinese).

[12]Jin ZR, Hu A, Shan XY, et al., 2023. A fractional-N CP-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS. Microelectr J, 132:105676.

[13]Liu GZ, Li B, Wei JH, et al., 2019. A radiation-hardened Sense-Switch pFLASH cell for FPGA. Microelectr Reliab, 103:113514.

[14]Liu GZ, Li B, Xiao ZQ, et al., 2020. The TID characteristics of a radiation hardened Sense-Switch pFLASH cell. IEEE Trans Dev Mater Reliab, 20(2):358-365.

[15]Liu GZ, Wei JH, Yu Z, et al., 2023. Programming mechanism and characteristics of Sense-Switch pFlash cells. Microelectr Reliab, 143:114953.

[16]Liu MQ, Xu XG, Zeng C, et al., 2022. A study on the influence of dose rate on total ionizing dose effect of anti-fuse field programmable gate array—The irradiation damage is attenuated at low dose rate. Front Phys, 10:1035846.

[17]Microchip Technology Inc., 2022. ProASIC3E Flash Family FPGAs Datasheet:75-77. https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/proasic-3-fpgas [Accessed on Mar. 30, 2023].

[18]Nadal J, Baghdadi A, 2021. Parallel and flexible 5G LDPC decoder architecture targeting FPGA. IEEE Trans Very Large Scale Integr Syst, 29(6):1141-1151.

[19]Park C, Yoon JS, Nam K, et al., 2023. Quantitative analysis of irregular channel shape effects on charge-trapping efficiency using massive 3D NAND data. Mater Sci Semicond Process, 157:107333.

[20]Shah A, Nayyar R, Sinha A, 2020. Silicon-proven timing signoff methodology using hazard-free robust path delay tests. IEEE Des Test, 37(4):7-13.

[21]Shan YE, Cao ZZ, Liu GZ, 2022. Research on eigenstate current control technology of Flash-based FPGA. J Semicond, 43(12):122401.

[22]Song SD, Liu GZ, Zhang HL, et al., 2021. Reliability evaluation on sense-switch p-channel Flash. J Semicond, 42(8):084101.

[23]Song SD, Liu GZ, He Q, et al., 2022. Combined effects of cycling endurance and total ionizing dose on floating gate memory cells. Chin Phys B, 31(5):056107.

[24]Suzuki D, Hanyu T, 2023. Design of an energy-efficient nonvolatile lookup table circuit using active-load-localized circuitry with self-terminated writing/reading. Jpn J Appl Phys, 62:SC1099.

[25]Swift GM, Rezgui S, George J, et al., 2004. Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs). IEEE Trans Nucl Sci, 51(6):3469-3474.

[26]Takahiro O, Hiroshi O, Osamu S, et al., 1999. Device characteristics of 0.35 μm P-channel DINOR Flash memory using band-to-band tunneling-induced hot electron (BBHE) programming. IEEE Trans Electron Dev, 46(9):1866-1871.

[27]Tan SXD, 2006. Symbolic analysis of analog circuits by Boolean logic operations. IEEE Trans Circ Syst II Expr Briefs, 53(11):1313-1317.

[28]Tian HN, Ibrahim Y, Chen R, et al., 2023. Evaluation of SEU impact on convolutional neural networks based on BRAM and CRAM in FPGAs. Microelectr Reliab, 144:114974.

[29]Wulf C, Willig M, Goehringer D, 2022. RTOS-supported low power scheduling of periodic hardware tasks in Flash-based FPGAs. Microprocess Microsyst, 92:104566.

[30]Inc. Xilinx, 2009. Virtex-4 FPGA Data Sheet: 31-32. https://docs.xilinx.com/v/u/en-US/DS302 [Accessed on Mar. 30, 2023].

[31]Zhang F, Guo CG, Zhang SF, et al., 2020. Research on hex programmable interconnect points test in island-style FPGA. Electronics, 9(12):2177.

[32]Zhang F, Guo CG, Zhang SF, et al., 2022. A genetic algorithm-based on-orbit self-repair implementation for SRAM based FPGAs. Expert Syst, 39(10):e13039.