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CLC number: TP393.02

On-line Access: 2026-03-23

Received: 2025-12-19

Revision Accepted: 2026-01-23

Crosschecked: 2026-03-23

Cited: 0

Clicked: 14

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Fan Zhang

https://orcid.org/0000-0001-7456-8377

Rui ZHENG

https://orcid.org/0009-0004-6458-5439

Jianliang SHEN

https://orcid.org/0009-0000-5647-043X

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ENGINEERING Information Technology & Electronic Engineering  2026 Vol.27 No.3 P.1-18

http://doi.org/10.1631/ENG.ITEE.2025.0180


De-blocking adaptive feedback control design for shared-buffer CIOQ switching architecture


Author(s):  Rui ZHENG, Jianliang SHEN, Fan ZHANG, Ping LV, Peijie LI, Yu SHAO, Zhengbin ZHU

Affiliation(s):  1. Information Engineering University, Zhengzhou 450001, China more

Corresponding email(s):   shenjianliang@outlook.com

Key Words:  Shared-buffer CIOQ switching architecture, Head-of-line (HOL) blocking, Congestion spreading, Adaptive feedback control (AFC), Peripheral component interconnect express (PCIe) interconnect protocol


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Rui ZHENG, Jianliang SHEN, Fan ZHANG, Ping LV, Peijie LI, Yu SHAO, Zhengbin ZHU. De-blocking adaptive feedback control design for shared-buffer CIOQ switching architecture[J]. Journal of Zhejiang University Science C, 2026, 27(3): 1-18.

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author="Rui ZHENG, Jianliang SHEN, Fan ZHANG, Ping LV, Peijie LI, Yu SHAO, Zhengbin ZHU",
journal="Journal of Zhejiang University Science C",
volume="27",
number="3",
pages="1-18",
year="2026",
publisher="Zhejiang University Press & Springer",
doi="10.1631/ENG.ITEE.2025.0180"
}

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%T De-blocking adaptive feedback control design for shared-buffer CIOQ switching architecture
%A Rui ZHENG
%A Jianliang SHEN
%A Fan ZHANG
%A Ping LV
%A Peijie LI
%A Yu SHAO
%A Zhengbin ZHU
%J Frontiers of Information Technology & Electronic Engineering
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%I Zhejiang University Press & Springer
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A1 - Rui ZHENG
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A1 - Ping LV
A1 - Peijie LI
A1 - Yu SHAO
A1 - Zhengbin ZHU
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DOI - 10.1631/ENG.ITEE.2025.0180


Abstract: 
To address the issues of head-of-line (HOL) blocking at the virtual output queue (VOQ) level, packet loss, and congestion spreading caused by buffer overflow in the shared-buffer-based combined input and output queued (CIOQ) switching architecture, while enhancing its performance and stability, we propose a de-blocking adaptive feedback control (AFC) design in this study. The introduction of the credit timeout detection mechanism (CTDM) enables the CIOQ to achieve theoretical 100% non-blocking state, effectively eliminating the impact of HOL blocking. With the combined effect of the proposed VOQ dynamic regulation algorithm (VDRA) and threshold dynamic adaptive algorithm (TDAA), it can reduce the risk of congestion spreading caused by buffer overflow and consequently improve the overall performance of the system. Both theoretical analysis and experimental results demonstrate that, under typical traffic conditions, the proposed design achieves a maximum throughput of 1499.66 Gb/s and a minimum latency of 83 ns. Additionally, the effective throughput ratio reaches 96.94%, with a data link layer packet (DLLP) loss ratio of merely 0.61% and a packet loss rate as low as 0.6%. In comparison with traditional CIOQ and input queued (IQ) switch architectures, the proposed design demonstrates improvements in throughput by 15.12% and 20.55%, and forwarding latency is reduced by 26.9% and 54.7%, respectively, and the system stability is stronger, which can fully satisfy the demand for data exchange in complex situations.

面向共享缓存CIOQ交换架构的去阻塞自适应反馈调节设计

郑锐1,沈剑良1,张帆2,吕平1,李沛杰1,邵宇1,朱正彬3
1信息工程大学,中国郑州市,450001
2复旦大学计算与智能创新学院,中国上海市,200433
3中国人民武装警察部队指挥学院,中国天津市,300250
摘要:为解决共享缓存组合输入输出排队(CIOQ)交换结构中存在的虚拟输出队列级别的队头(HOL)阻塞、缓存溢出丢包及拥塞扩散等问题,同时提升性能和稳定性,本文提出去阻塞自适应反馈调节设计。通过引入基于信用量的超时检测机制,实现理论上的100%无阻塞,大幅消除了HOL阻塞的影响。在所提虚拟输出队列动态调节算法和阈值动态自适应算法共同作用下,该设计能够降低缓存溢出引发的拥塞扩散风险,从而提升系统整体性能。理论分析与实验结果表明,在典型流量场景下,所提设计的最大吞吐量可达1499.66Gb/s,最低时延为83 ns。此外,有效吞吐量占比高达96.94%,数据链路层包损失占比仅为0.61%,丢包率低至0.6%。相较于传统CIOQ架构和输入排队交换架构,所提设计的吞吐量分别提升15.12%和20.55%,转发时延分别缩短26.9%和54.7%,且系统稳定性更强,可充分满足复杂场景下的数据交换需求。

关键词:共享缓存组合输入输出排队交换架构;队头(HOL)阻塞;拥塞扩散;自适应反馈调节;PCIe互连协议

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