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CLC number: TN919.8

On-line Access: 2013-06-04

Received: 2012-08-28

Revision Accepted: 2013-03-06

Crosschecked: 2013-05-13

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Journal of Zhejiang University SCIENCE C 2013 Vol.14 No.6 P.449-463

http://doi.org/10.1631/jzus.C1200250


High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding


Author(s):  Kai Huang, De Ma, Rong-jie Yan, Hai-tong Ge, Xiao-lang Yan

Affiliation(s):  Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China; more

Corresponding email(s):   huangk@vlsi.zju.edu.cn, yrj@ios.ac.cn

Key Words:  H.264/AVC, Context-based adaptive binary arithmetic coding (CABAC), Decoder, VLSI


Kai Huang, De Ma, Rong-jie Yan, Hai-tong Ge, Xiao-lang Yan. High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding[J]. Journal of Zhejiang University Science C, 2013, 14(6): 449-463.

@article{title="High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding",
author="Kai Huang, De Ma, Rong-jie Yan, Hai-tong Ge, Xiao-lang Yan",
journal="Journal of Zhejiang University Science C",
volume="14",
number="6",
pages="449-463",
year="2013",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C1200250"
}

%0 Journal Article
%T High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding
%A Kai Huang
%A De Ma
%A Rong-jie Yan
%A Hai-tong Ge
%A Xiao-lang Yan
%J Journal of Zhejiang University SCIENCE C
%V 14
%N 6
%P 449-463
%@ 1869-1951
%D 2013
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1200250

TY - JOUR
T1 - High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding
A1 - Kai Huang
A1 - De Ma
A1 - Rong-jie Yan
A1 - Hai-tong Ge
A1 - Xiao-lang Yan
J0 - Journal of Zhejiang University Science C
VL - 14
IS - 6
SP - 449
EP - 463
%@ 1869-1951
Y1 - 2013
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1200250


Abstract: 
context-based adaptive binary arithmetic coding (CABAC) is the major entropy-coding algorithm employed in h.264/AVC. In this paper, we present a new VLSI architecture design for an h.264/AVC CABAC decoder, which optimizes both decode decision and decode bypass engines for high throughput, and improves context model allocation for efficient external memory access. Based on the fact that the most possible symbol (MPS) branch is much simpler than the least possible symbol (LPS) branch, a newly organized decode decision engine consisting of two serially concatenated MPS branches and one LPS branch is proposed to achieve better parallelism at lower timing path cost. A look-ahead context index (ctxIdx) calculation mechanism is designed to provide the context model for the second MPS branch. A head-zero detector is proposed to improve the performance of the decode bypass engine according to UEGk encoding features. In addition, to lower the frequency of memory access, we reorganize the context models in external memory and use three circular buffers to cache the context models, neighboring information, and bit stream, respectively. A pre-fetching mechanism with a prediction scheme is adopted to load the corresponding content to a circular buffer to hide external memory latency. Experimental results show that our design can operate at 250 MHz with a 20.71k gate count in SMIC18 silicon technology, and that it achieves an average data decoding rate of 1.5 bins/cycle.

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Reference

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[7]Liao, Y.H., Li, G.L., Chang, T.S., 2012. A highly efficient VLSI architecture for H.264/AVC level 5.1 CABAC decoder. IEEE Trans. Circ. Syst. Video Technol., 22(2):272-281.

[8]Ma, D., Huang, K., Chen, H.F., Yu, M., Yan, X.L., 2011. Mixed increasing filter pipeline design for H.264/AVC deblocking filter. J. Zhejiang Univ. (Eng. Sci.), 45(7):1206-1214 (in Chinese).

[9]Shi, B., Zheng, W., Lee, H.S., Li, D.X., Zhang, M., 2008. Pipelined Architecture Design of H.264/AVC CABAC Real-Time Decoding. 4th IEEE Int. Conf. on Circuits and Systems for Communications, p.492-496.

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[11]Yang, Y.C., Guo, J.I., 2009. High-throughput H.264/AVC high-profile CABAC decoder for HDTV applications. IEEE Trans. Circ. Syst. Video Technol., 19(9):1395-1399.

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[13]Yu, W., He, Y., 2005. A high performance CABAC decoding architecture. IEEE Trans. Consum. Electron., 51(4):1352-1359.

[14]Yuan, T.C., 2008. A Novel Pipeline Architecture for H.264/AVC CABAC Decoder. IEEE Asia Pacific Conf. on Circuit and Systems, p.208-311.

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