CLC number: TN919.8
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2009-05-27
Cited: 1
Clicked: 6096
Hu WEI, Tao LIN, Zheng-hui LIN. Parallel processing architecture of H.264 adaptive deblocking filters[J]. Journal of Zhejiang University Science A, 2009, 10(8): 1160-1168.
@article{title="Parallel processing architecture of H.264 adaptive deblocking filters",
author="Hu WEI, Tao LIN, Zheng-hui LIN",
journal="Journal of Zhejiang University Science A",
volume="10",
number="8",
pages="1160-1168",
year="2009",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.A0820502"
}
%0 Journal Article
%T Parallel processing architecture of H.264 adaptive deblocking filters
%A Hu WEI
%A Tao LIN
%A Zheng-hui LIN
%J Journal of Zhejiang University SCIENCE A
%V 10
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%P 1160-1168
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%D 2009
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.A0820502
TY - JOUR
T1 - Parallel processing architecture of H.264 adaptive deblocking filters
A1 - Hu WEI
A1 - Tao LIN
A1 - Zheng-hui LIN
J0 - Journal of Zhejiang University Science A
VL - 10
IS - 8
SP - 1160
EP - 1168
%@ 1673-565X
Y1 - 2009
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.A0820502
Abstract: In h.264, computational complexity and memory access of deblocking filters are variable, dependent on video contents. This paper proposes a VLSI architecture of deblocking filters with adaptive dynamic power, which avoids redundant computations and memory accesses by precluding the blocks that can be skipped. The vertical and horizontal edges are simultaneously processed in an advanced scan order to speed up the decoder. As a result, dynamic power of the proposed architecture can be reduced adaptively (up to about 89%) for different videos, and the off-chip memory access is improved when compared to previous designs. Moreover, the processing capability of the proposed architecture is in particular appropriate for real-time deblocking of high-definition television (HDTV, 1920×1080 pixels/frame, 60 frames/s video signals) video operation at 62 MHz. Using the proposed architecture, power can be reduced by up to about 89% and processing time by from 25% to 81% compared with previous designs.
[1] Arbelo, C., Kanstein, A., Lopez, S., 2007. Mapping Control-intensive Video Kernels onto a Coarse-grain Reconfigurable Architecture: The H.264/AVC Deblocking Filter. IEEE Conf. on Design, Automation and Test, p.1-6.
[2] Chen, C.M., Chen, C.H., 2005. An Efficient Architecture for Deblocking Filter in H.264/AVC Video Coding. IASTED Int. Conf. on Computer Graphics and Imaging, p.177-181.
[3] Chen, C.M., Chen, C.H., 2006. Window Architecture for Deblocking Filter in H.264/AVC. IEEE Int. Symp. on Signal Processing and Information Technology, p.338-342.
[4] Chen, C.M., Chen, C.H., 2007. An efficient pipeline architecture for deblocking filter in H.264/AVC. IEICE Trans. Inf. Syst., E90-D(1):99-107.
[5] Cheng, C.C., Chang, T.S., 2005. A Hardware Efficient Deblocking Filter for H.264/AVC. IEEE Conf. on Consumer Electronics, p.235-236.
[6] Hao, W.N., Radetzki, M., 2008. A Data Traffic Efficient H.264 Deblocking IP. IEEE Int. Symp. on Circuits and Systems, p.3430-3433.
[7] Huang, Y.W., Chen, T.W., Hsieh, B.Y., Wang, T.C., Chang, T.H., Chen, L.G., 2003. Architecture Design for Deblocking Filter in H.264/JVT/AVC. IEEE Conf. on Multimedia and Expo, p.693-696.
[8] Huang, Y.W., Hsieh, B.Y., Chen, T.C., Chen, L.G., 2005. Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder. IEEE Trans. Circuits Syst. Video Technol., 15(3):378-401.
[9] Li, L.F., Goto, S., Ikenaga, T., 2005. A highly parallel architecture for deblocking filter in H.264/AVC. IEICE Trans. Inf. Syst., E88-D(7):1623-1629.
[10] Liu, T.M., Lee, W.P., Lee, C.Y., 2007. An in/post-loop deblocking filter with hybrid filtering schedule. IEEE Trans. Circuits Syst. Video Technol., 17(7):937-943.
[11] Lou, J., Jagmohan, A., He, D.K., Lu, L.G., Sun, M.T., 2007. High Speed H.264 High Profile Deblocking Using Statistical Analysis and Logic Optimization. Int. Conf. on Multimedia and Expo, p.1918-1921.
[12] Min, K.Y., Chong, J.W., 2007. A Memory and Performance Optimized Architecture of Deblocking Filter in H.264/AVC. IEEE Conf. on Multimedia and Ubiquitous Engineering, p.220-225.
[13] Sullivan, G., Topiwala, P., Luthra, A., 2004. The H.264/AVC Advanced Video Coding Standard: Overview and Introduction to the Fidelity Range Extensions. SPIE, 5558:454.
[14] Vladimir, C., Ivan, M., 2007. Area-time Tradeoffs in H.264/ AVC Deblocking Filter Design for Mobile Devices. ISSPA, p.1-4.
[15] Warrington, S., Shojania, H., Sudharsanan, S., 2006. Performance Improvement of the H.264/AVC Deblocking Filter Using SIMD Instructions. IEEE Proc. ISCAS, p.2697-2700.
[16] Xu, K., Choy, C.S., 2008. A five-stage pipeline, 204 cycles/ MB, single-port SRAM-based deblocking filter for H.264/AVC. IEEE Trans. Circuits Syst. Video Technol., 18(3):363-377.
[17] Zhao, S., Lu, C., 2007. VLSI Design for De-blocking Filter of H.264 Decoder. IEEE Conf. on ASIC, p.786-789.
[18] Zhao, Y.X., Jiang, A.P., 2007. An effective parallel processing architecture for deblocking filter in H.264. Acta Sci. Nat. Univ. Pekin., 43(5):649-653 (in Chinese).
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