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Journal of Zhejiang University SCIENCE A 2008 Vol.9 No.12 P.1644~1655

http://doi.org/10.1631/jzus.A0820052


A parallel memory architecture for video coding


Author(s):  Jian-ying PENG, Xiao-lang YAN, De-xian LI, Li-zhong CHEN

Affiliation(s):  Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   pengjy@vlsi.zju.edu.cn, yan@vlsi.zju.edu.cn

Key Words:  Single instruction multiple data (SIMD), Video coding, Parallel memory, Skewing scheme


Jian-ying PENG, Xiao-lang YAN, De-xian LI, Li-zhong CHEN. A parallel memory architecture for video coding[J]. Journal of Zhejiang University Science A, 2008, 9(12): 1644~1655.

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author="Jian-ying PENG, Xiao-lang YAN, De-xian LI, Li-zhong CHEN",
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%DOI 10.1631/jzus.A0820052

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T1 - A parallel memory architecture for video coding
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A1 - De-xian LI
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J0 - Journal of Zhejiang University Science A
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SP - 1644
EP - 1655
%@ 1673-565X
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.A0820052


Abstract: 
To efficiently exploit the performance of single instruction multiple data (SIMD) architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel skewing schemes to provide conflict-free access to adjacent elements (8-bit and 16-bit data types) or with power-of-two intervals in both horizontal and vertical directions, which were not possible in previous parallel memory architectures. Area consumptions and delay estimations are given respectively with 4, 8 and 16 memory modules. Under a 0.18-μm CMOS technology, the synthesis results show that the proposed system can achieve 230 MHz clock frequency with 16 memory modules at the cost of 19k gates when read and write latencies are 3 and 2 clock cycles, respectively. We implement the proposed parallel memory architecture on a video signal processor (VSP). The results show that VSP enhanced with the proposed architecture achieves 1.28× speedups for H.264 real-time decoding.

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