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CLC number: TN919.8

On-line Access: 2008-05-10

Received: 2007-08-30

Revision Accepted: 2007-12-14

Crosschecked: 0000-00-00

Cited: 4

Clicked: 3416

Citations:  Bibtex RefMan EndNote GB/T7714

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Journal of Zhejiang University SCIENCE A 2008 Vol.9 No.6 P.822~832

http://doi.org/10.1631/jzus.A071460


High throughput bandwidth optimized VLSI design for motion compensation in AVS HDTV decoder


Author(s):  Kai LUO, Dong-xiao LI, Ming ZHANG

Affiliation(s):  Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   luokai82@gmail.com, lidx@zju.edu.cn

Key Words:  Audio Video coding Standard (AVS), Motion compensation (MC), Interpolation, VLSI, Architecture


Kai LUO, Dong-xiao LI, Ming ZHANG. High throughput bandwidth optimized VLSI design for motion compensation in AVS HDTV decoder[J]. Journal of Zhejiang University Science A, 2008, 9(6): 822~832.

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Abstract: 
In this paper we present a motion compensation (MC) design for the newest audio Video coding Standard (AVS) of China. Because of compression-efficient techniques of variable block size (VBS) and sub-pixel interpolation, intensive pixel calculation and huge memory access are required. We propose a parallel serial filtering mixed luma interpolation data flow and a three-stage multiplication free chroma interpolation scheme. Compared to the conventional designs, the integrated architecture supports about 2.7 times filtering throughput. The proposed MC design utilizes Vertical Z processing order for reference data re-use and saves up to 30% memory bandwidth. The whole design requires 44.3k gates when synthesized at 108 MHz clock frequency using 0.18-μm CMOS technology and can support up to 1920×1088@30 fps AVS HDTV video decoding.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

[1] AVS Reference Software, 2007. Ftp://159.226.42.57/public/avs_doc/avs_software

[2] AVS Workgroup, 2004. Information Technology—Advanced Audio Video Coding Standard, Part 2: Video.

[3] Chen, T.C., Huang, Y.W., Chen, L.G., 2004. Fully Utilized and Reusable Architecture for Fractional Motion Estimation of H.264/AVC. Proc. ICASSP, p.9-12.

[4] Deng, L., Gao, W., Hu, M.Z., Ji, Z.Z., 2004. An efficient VLSI implementation for MC interpolation of AVS standard. LNCS, 3333:200-206.

[5] Fan, L., Ma, S.W., Wu, F., 2004. Overview of AVS Video Standard. Proc. ICME, p.423-426.

[6] He, W.F., Mao, Z.G., Wang, J.X., Wang, D.F., 2003. Design and Implementation of Motion Compensation for MPEG-4 AS Profile Streaming Video Decoding. Proc. ASICON, p.942-945.

[7] Hyun, C.J., Kim, S.D., Sunwoo, M.H., 2006. Efficient Memory Reuse and Sub-Pixel Interpolation Algorithms for ME/MC of H.264/AVC. IEEE Workshop on Signal Processing Systems Design and Implementation, p.377-382.

[8] Jia, H.Z., Zhang, P., Xie, D., Gao, W., 2006. An AVS HDTV video decoder architecture employing efficient HW/SW partitioning. IEEE Trans. on Consumer Electronics, 52(4):1447-1453.

[9] Lie, W.N., Yeh, H.C., Lin, T.C.I., Chen, C.F., 2005. Hardware-Efficient Computing Architecture for Motion Compensation Interpolation in H.264 Video Coding. Proc. ISCAS, p.2136-2139.

[10] Song, Y., Liu, Z.Y., Goto, S., Ikenaga, T., 2005. A VLSI Architecture for Motion Compensation Interpolation in H.264/AVC. Proc. ASICON, p.279-282.

[11] Tsai, C.Y., Chen, T.C., Chen, T.W., Chen, L.G., 2005. Bandwidth Optimized Motion Compensation Hardware Design for H.264/AVC HDTV Decoder. Proc. 48th Midwest Symp. on Circuits and Systems, p.1199-1202.

[12] Wang, R.G., Huang, C., Li, J.T., Shen, Y.F., 2004. Sub-Pixel motion Compensation Interpolation Filter in AVS. Proc. ICME, p.93-96.

[13] Wang, R.G., Li, J.T., Huang, C., Zhang, Y.D., 2005. A sub-pixel motion compensation interpolation method and its high performance VLSI design. Chin. J. Computers, 28(12):2052-2058 (in Chinese).

[14] Wang, S.Z., Lin, T.A., Liu, T.M., Lee, C.Y., 2005. A New Motion Compensation Design for H.264/AVC Decoder. Proc. ISCAS, p.4558-4561.

[15] Yu, L., Yi, F., Dong, J., Zhang, C.X., 2005. Overview of AVS—Video: Tools, Performance and Complexity. Proc. SPIE, 5960:679-690.

[16] Zhang, N.R., Li, M., Wu, C.W., 2006. High Performance and Efficient Bandwidth Motion Compensation VLSI Design for H.264/AVC Decoder. Proc. ICSICT, p.1896-1898.

[17] Zheng, J.H., Deng, L., Zhang, P., Xie, D., 2006. An efficient VLSI architecture for motion compensation of AVS HDTV decoder. J. Computer Sci. Technol., 21(3):370-377.

[18] Zhou, D.J., Liu, P.L., 2007. A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264. Proc. ISCAS, p.2910-2913.

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