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CLC number: TN919.8

On-line Access: 2008-05-10

Received: 2007-08-30

Revision Accepted: 2007-12-14

Crosschecked: 0000-00-00

Cited: 4

Clicked: 3416

Citations:  Bibtex RefMan EndNote GB/T7714

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Journal of Zhejiang University SCIENCE A 2008 Vol.9 No.6 P.822~832


High throughput bandwidth optimized VLSI design for motion compensation in AVS HDTV decoder

Author(s):  Kai LUO, Dong-xiao LI, Ming ZHANG

Affiliation(s):  Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   luokai82@gmail.com, lidx@zju.edu.cn

Key Words:  Audio Video coding Standard (AVS), Motion compensation (MC), Interpolation, VLSI, Architecture

Kai LUO, Dong-xiao LI, Ming ZHANG. High throughput bandwidth optimized VLSI design for motion compensation in AVS HDTV decoder[J]. Journal of Zhejiang University Science A, 2008, 9(6): 822~832.

@article{title="High throughput bandwidth optimized VLSI design for motion compensation in AVS HDTV decoder",
author="Kai LUO, Dong-xiao LI, Ming ZHANG",
journal="Journal of Zhejiang University Science A",
publisher="Zhejiang University Press & Springer",

%0 Journal Article
%T High throughput bandwidth optimized VLSI design for motion compensation in AVS HDTV decoder
%A Kai LUO
%A Dong-xiao LI
%J Journal of Zhejiang University SCIENCE A
%V 9
%N 6
%P 822~832
%@ 1673-565X
%D 2008
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.A071460

T1 - High throughput bandwidth optimized VLSI design for motion compensation in AVS HDTV decoder
A1 - Kai LUO
A1 - Dong-xiao LI
A1 - Ming ZHANG
J0 - Journal of Zhejiang University Science A
VL - 9
IS - 6
SP - 822
EP - 832
%@ 1673-565X
Y1 - 2008
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.A071460

In this paper we present a motion compensation (MC) design for the newest audio Video coding Standard (AVS) of China. Because of compression-efficient techniques of variable block size (VBS) and sub-pixel interpolation, intensive pixel calculation and huge memory access are required. We propose a parallel serial filtering mixed luma interpolation data flow and a three-stage multiplication free chroma interpolation scheme. Compared to the conventional designs, the integrated architecture supports about 2.7 times filtering throughput. The proposed MC design utilizes Vertical Z processing order for reference data re-use and saves up to 30% memory bandwidth. The whole design requires 44.3k gates when synthesized at 108 MHz clock frequency using 0.18-μm CMOS technology and can support up to 1920×1088@30 fps AVS HDTV video decoding.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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