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CLC number: TN919.8; TP37

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Received: 2008-02-18

Revision Accepted: 2008-04-08

Crosschecked: 2008-11-10

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Journal of Zhejiang University SCIENCE A 2008 Vol.9 No.12 P.1638-1643


Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder

Author(s):  Wan-yi LI, Lu YU

Affiliation(s):  Institute of Information and Communication Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   leeswane8621@hotmail.com

Key Words:  VLSI architecture, Interpolation, AVS HDTV

Wan-yi LI, Lu YU. Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder[J]. Journal of Zhejiang University Science A, 2008, 9(12): 1638-1643.

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author="Wan-yi LI, Lu YU",
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publisher="Zhejiang University Press & Springer",

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T1 - Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder
A1 - Wan-yi LI
A1 - Lu YU
J0 - Journal of Zhejiang University Science A
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EP - 1643
%@ 1673-565X
Y1 - 2008
PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.A0820112

In this paper, we propose an effective VLSI architecture of sub-pixel interpolation for motion compensation in the AVS HDTV decoder. To utilize the similar arithmetical operations of 15 luma sub-pixel positions, three types of interpolation filters are proposed. A simplified multiplier is presented due to the limited range of input in the chroma interpolation process. To improve the processing throughput, a parallel and pipelined computing architecture is adopted. The simulation results show that the proposed hardware implementation can satisfy the real-time constraint for the AVS HDTV (1 920×1 088) 30 fps decoder by operating at 108 MHz with 38.18k logic gates. Meanwhile, it costs only 216 cycles to accomplish one macroblock, which means the B frame sub-pixel interpolation can be realized by using only one set of the proposed architecture under real-time constraints.

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