Full Text:   <1901>

CLC number: TN919.8; TP37

On-line Access: 

Received: 2008-02-18

Revision Accepted: 2008-04-08

Crosschecked: 2008-11-10

Cited: 0

Clicked: 3213

Citations:  Bibtex RefMan EndNote GB/T7714

-   Go to

Article info.
1. Reference List
Open peer comments

Journal of Zhejiang University SCIENCE A 2008 Vol.9 No.12 P.1638~1643

http://doi.org/10.1631/jzus.A0820112


Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder


Author(s):  Wan-yi LI, Lu YU

Affiliation(s):  Institute of Information and Communication Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   leeswane8621@hotmail.com

Key Words:  VLSI architecture, Interpolation, AVS HDTV


Wan-yi LI, Lu YU. Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder[J]. Journal of Zhejiang University Science A, 2008, 9(12): 1638~1643.

@article{title="Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder",
author="Wan-yi LI, Lu YU",
journal="Journal of Zhejiang University Science A",
volume="9",
number="12",
pages="1638~1643",
year="2008",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.A0820112"
}

%0 Journal Article
%T Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder
%A Wan-yi LI
%A Lu YU
%J Journal of Zhejiang University SCIENCE A
%V 9
%N 12
%P 1638~1643
%@ 1673-565X
%D 2008
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.A0820112

TY - JOUR
T1 - Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder
A1 - Wan-yi LI
A1 - Lu YU
J0 - Journal of Zhejiang University Science A
VL - 9
IS - 12
SP - 1638
EP - 1643
%@ 1673-565X
Y1 - 2008
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.A0820112


Abstract: 
In this paper, we propose an effective VLSI architecture of sub-pixel interpolation for motion compensation in the AVS HDTV decoder. To utilize the similar arithmetical operations of 15 luma sub-pixel positions, three types of interpolation filters are proposed. A simplified multiplier is presented due to the limited range of input in the chroma interpolation process. To improve the processing throughput, a parallel and pipelined computing architecture is adopted. The simulation results show that the proposed hardware implementation can satisfy the real-time constraint for the AVS HDTV (1 920×1 088) 30 fps decoder by operating at 108 MHz with 38.18k logic gates. Meanwhile, it costs only 216 cycles to accomplish one macroblock, which means the B frame sub-pixel interpolation can be realized by using only one set of the proposed architecture under real-time constraints.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

[1] AVS (Audio Video Coding Standard Workgroup of China), 2003. Video Coding Standard FCD1.0.

[2] Chen, T.C., Huang, Y.W., Chen, L.G., 2004. Fully Utilized and Reusable Architecture for Fractional Motion Estimation of H.264/AVC. Proc. IEEE ICASSP, 5:9-12.

[3] Deng, L., Gao, W., Hu, M.Z., Ji, Z.Z., 2004. An Efficient VLSI Implementation for MC Interpolation of AVS Standard. Advances in Multimedia Information Processing, p.200-206.

[4] Horowitz, M., Joch, A., Kossentini, F., Hallapuro, A., 2003. H.264/AVC baseline profile decoder complexity analysis. IEEE Trans. on Circuits Syst. Video Technol., 13(7):704-716.

[5] Li, Y., Qu, Y.M., He, Y., 2007. Memory Cache Based Motion Compensation Architecture for HDTV H.264/AVC Decoder. IEEE Int. Symp. on Circuits and Systems, p.2906-2909.

[6] Ling, N., Wang, N.T., 2003. A real-time video decoder for digital HDTV. J. VLSI Signal Processing, 33(3):295-306.

[7] Mizosoe, H., Yoshida, D., Nakamura, T., 2007. A single chip H.264/AVC HDTV encoder/decoder/transcoder system LSI. IEEE Trans. on Consum. Electron., 53(2):630-635.

[8] Song, Y., Liu, Z.Y., Goto, S., Ikenaga, T., 2005. A VLSI Architecture for Motion Compensation Interpolation in H.264/AVC. 6th Int. Conf. on ASIC, 1:279-282.

[9] Tsai, C.Y., Chen, T.C., Chen, T.W., Chen, L.G., 2005. Bandwidth Optimized Motion Compensation Hardware Design for H.264/AVC HDTV Decoder. 48th Midwest Symp. on Circuits and Systems, 2:1199-1202.

[10] Wang, R.G., Huang, C., Li, J.T., Shen, Y.F., 2004. Sub-pixel Motion Compensation Interpolation Filter in AVS. IEEE Int. Conf. on Multimedia and Expo, 1:93-96.

[11] Wang, S.Z., Lin, T.A., Liu, T.M., Lee, C.Y., 2005. A New Motion Compensation Design for H.264/AVC Decoder. Proc. IEEE Int. Symp. on Circuits and Systems, 5:4558-4561.

[12] Zheng, J.H., Deng, L., Zhang, P., Xie, D., 2006. An efficient VLSI architecture for motion compensation of AVS HDTV decoder. J. Comput. Sci. Technol., 21(3):370-377.

Open peer comments: Debate/Discuss/Question/Opinion

<1>

Please provide your name, email address and a comment





Journal of Zhejiang University-SCIENCE, 38 Zheda Road, Hangzhou 310027, China
Tel: +86-571-87952783; E-mail: cjzhang@zju.edu.cn
Copyright © 2000 - Journal of Zhejiang University-SCIENCE