CLC number: TN402; TP36
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2008-10-28
Cited: 3
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Kai HUANG, Xiao-lang YAN, Sang-il HAN, Soo-ik CHAE, Ahmed A. JERRAYA, Katalin POPOVICI, Xavier GUERIN, Lisane BRISOLARA, Luigi CARRO. Gradual refinement for application-specific MPSoC design from Simulink model to RTL implementation[J]. Journal of Zhejiang University Science A, 2009, 10(2): 151-164.
@article{title="Gradual refinement for application-specific MPSoC design from Simulink model to RTL implementation",
author="Kai HUANG, Xiao-lang YAN, Sang-il HAN, Soo-ik CHAE, Ahmed A. JERRAYA, Katalin POPOVICI, Xavier GUERIN, Lisane BRISOLARA, Luigi CARRO",
journal="Journal of Zhejiang University Science A",
volume="10",
number="2",
pages="151-164",
year="2009",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.A0820085"
}
%0 Journal Article
%T Gradual refinement for application-specific MPSoC design from Simulink model to RTL implementation
%A Kai HUANG
%A Xiao-lang YAN
%A Sang-il HAN
%A Soo-ik CHAE
%A Ahmed A. JERRAYA
%A Katalin POPOVICI
%A Xavier GUERIN
%A Lisane BRISOLARA
%A Luigi CARRO
%J Journal of Zhejiang University SCIENCE A
%V 10
%N 2
%P 151-164
%@ 1673-565X
%D 2009
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.A0820085
TY - JOUR
T1 - Gradual refinement for application-specific MPSoC design from Simulink model to RTL implementation
A1 - Kai HUANG
A1 - Xiao-lang YAN
A1 - Sang-il HAN
A1 - Soo-ik CHAE
A1 - Ahmed A. JERRAYA
A1 - Katalin POPOVICI
A1 - Xavier GUERIN
A1 - Lisane BRISOLARA
A1 - Luigi CARRO
J0 - Journal of Zhejiang University Science A
VL - 10
IS - 2
SP - 151
EP - 164
%@ 1673-565X
Y1 - 2009
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.A0820085
Abstract: The application-specific multiprocessor system-on-chip (MPSoC) architecture is becoming an attractive solution to deal with increasingly complex embedded applications, which require both high performance and flexible programmability. As an effective method for MPSoC development, we present a gradual refinement flow starting from a high-level simulink model to a synthesizable and executable hardware and software specification. The proposed methodology consists of five different abstract levels: simulink combined algorithm and architecture model (CAAM), virtual architecture (VA), transactional accurate architecture (TA), virtual prototype (VP) and field-programmable gate array (FPGA) emulation. Experimental results of motion-JPEG and h.264 show that the proposed gradual refinement flow can generate various MPSoC architectures from an original simulink model, allowing processor, communication and tasks design space exploration.
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