CLC number: TN43
On-line Access: 2015-08-04
Received: 2014-12-28
Revision Accepted: 2015-06-07
Crosschecked: 2015-07-20
Cited: 1
Clicked: 7041
Shou-biao Tan, Wen-juan Lu, Chun-yu Peng, Zheng-ping Li, You-wu Tao, Jun-ning Chen. Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier[J]. Frontiers of Information Technology & Electronic Engineering, 2015, 16(8): 700-706.
@article{title="Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier",
author="Shou-biao Tan, Wen-juan Lu, Chun-yu Peng, Zheng-ping Li, You-wu Tao, Jun-ning Chen",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="16",
number="8",
pages="700-706",
year="2015",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1400439"
}
%0 Journal Article
%T Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier
%A Shou-biao Tan
%A Wen-juan Lu
%A Chun-yu Peng
%A Zheng-ping Li
%A You-wu Tao
%A Jun-ning Chen
%J Frontiers of Information Technology & Electronic Engineering
%V 16
%N 8
%P 700-706
%@ 2095-9184
%D 2015
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1400439
TY - JOUR
T1 - Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier
A1 - Shou-biao Tan
A1 - Wen-juan Lu
A1 - Chun-yu Peng
A1 - Zheng-ping Li
A1 - You-wu Tao
A1 - Jun-ning Chen
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 16
IS - 8
SP - 700
EP - 706
%@ 2095-9184
Y1 - 2015
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.1400439
Abstract: A multi-stage dual replica bit-line delay (MDRBD) technique is proposed for reducing access time by suppressing the sense-amplifier enable (SAE) timing variation of low voltage static random-access memory (SRAM) applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-line (RBL) capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology (Taiwan Semiconductor Manufacturing Company, Taiwan).
[1]Amrutur, B.S., Horowitz, M.A., 1998. A replica technique for wordline and sense control in low-power SRAM’s. IEEE J. Sol.-State Circ., 33(8):1208-1219.
[2]Arandilla, C.D.C., Madamba, J.A.R., 2011. Comparison of replica bitline technique and chain delay technique as read timing control for low-power asynchronous SRAM. Proc. 5th Asia Modelling Symp., p.275-278.
[3]Arslan, U., McCartney, M.P., Bhargava, M., et al., 2008. Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. Proc. IEEE Custom Integrated Circuits Conf., p.415-418.
[4]Chang, I.J., Mohapatra, D., Roy, K., 2011. A priority-based 6T/8T hybrid SRAM architecture for aggressive voltage scaling in video applications. IEEE Trans. Circ. Syst. Video Technol., 21(2):101-112.
[5]Gammie, G., Ickes, N., Sinangil, M.E., et al., 2011. A 28 nm 0.6 V low-power DSP for mobile applications. Proc. IEEE Int. Solid-State Circuits Conf., p.132-134.
[6]Johnson, J.B., Hook, T.B., Lee, Y.M., 2008. Analysis and modeling of threshold voltage mismatch for CMOS at 65 nm and beyond. IEEE Electr. Dev. Lett., 29(7):802-804.
[7]Kawasumi, A., Takeyama, Y., Hirabayashi, O., et al., 2012. Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction. Proc. IEEE Int. Conf. on IC Design & Technology, p.1-4.
[8]Keyes, R.W., 1975. Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics. IEEE J. Sol.-State Circ., 10(4):245-247.
[9]Komatsu, S., Yamaoka, M., Morimoto, M., et al., 2009. A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. Proc. IEEE Custom Integrated Circuits Conf., p.701-704.
[10]Li, Y., Wen, L., Zhang, Y., et al., 2014. An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. IEICE Electron. Expr., 11(3):1-6.
[11]Lovett, S.J., Gibbs, G.A., Pancholy, A., 2000. Yield and matching implications for static RAM memory array sense-amplifier design. IEEE J. Sol.-State Circ., 35(8):1200-1204.
[12]Niki, Y., Kawasumi, A., Suzuki, A., et al., 2010. A digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers. Proc. IEEE Asian Solid State Circuits Conf., p.1-4.
[13]Niki, Y., Kawasumi, A., Suzuki, A., et al., 2011. A digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers. IEEE J. Sol.-State Circ., 46(11):2545-2551.
[14]Osada, K., Shin, J., Khan, M., et al., 2001. Universal-VDD 0.65-2.0 V 32 KB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell. Proc. IEEE Int. Solid-State Circuits Conf., p.168-169.
[15]Pelgrom, M.J.M., Duinmaijer, A.C.J., Welbers, A.P.G., 1989. Matching properties of MOS transistors. IEEE J. Sol.-State Circ., 24(5):1433-1439.
[16]Song, T., Lee, S.M., Choi, J., et al., 2010. A robust latch-type sense amplifier using adaptive latch resistance. Proc. IEEE Int. Conf. on IC Design and Technology, p.182-185.
[17]Wu, J., Zhu, J., Xia, Y., et al., 2014. A multiple-stage parallel replica-bitline delay addition technique for reducing timing variation of SRAM sense amplifiers. IEEE Trans. Circ. Syst. II, 61(4):264-268.
Open peer comments: Debate/Discuss/Question/Opinion
<1>