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CLC number: TN4

On-line Access: 2012-06-05

Received: 2011-09-13

Revision Accepted: 2012-02-17

Crosschecked: 2012-04-09

Cited: 3

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Journal of Zhejiang University SCIENCE C 2012 Vol.13 No.6 P.460-471


High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility

Author(s):  Hossein Aghababa, Behjat Forouzandeh, Ali Afzali-Kusha

Affiliation(s):  Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran 14395, Iran

Corresponding email(s):   h.aghababa@ece.ut.ac.ir

Key Words:  High-performance circuit, Low-leakage circuit, Manufacturing process variation, CMOS integrated circuit

Hossein Aghababa, Behjat Forouzandeh, Ali Afzali-Kusha. High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility[J]. Journal of Zhejiang University Science C, 2012, 13(6): 460-471.

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%T High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility
%A Hossein Aghababa
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%P 460-471
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%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1100273

T1 - High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility
A1 - Hossein Aghababa
A1 - Behjat Forouzandeh
A1 - Ali Afzali-Kusha
J0 - Journal of Zhejiang University Science C
VL - 13
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%@ 1869-1951
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PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1100273

We propose a modeling methodology for both leakage power consumption and delay of basic CMOS digital gates in the presence of threshold voltage and mobility variations. The key parameters in determining the leakage and delay are OFF and ON currents, respectively, which are both affected by the variation of the threshold voltage. Additionally, the current is a strong function of mobility. The proposed methodology relies on a proper modeling of the threshold voltage and mobility variations, which may be induced by any source. Using this model, in the plane of threshold voltage and mobility, we determine regions for different combinations of performance (speed) and leakage. Based on these regions, we discuss the trade-off between leakage and delay where the leakage-delay-product is the optimization objective. To assess the accuracy of the proposed model, we compare its predictions with those of HSPICE simulations for both basic digital gates and ISCAS85 benchmark circuits in 45-, 65-, and 90-nm technologies.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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