Full Text:  <592>

CLC number: TN432

On-line Access: 2017-05-24

Received: 2015-11-15

Revision Accepted: 2016-03-02

Crosschecked: 2017-04-27

Cited: 0

Clicked: 608

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Feng Zhang

http://orcid.org/0000-0003-2316-0392

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Frontiers of Information Technology & Electronic Engineering  2017 Vol.18 No.5 P.729-737

10.1631/FITEE.1500410


Wide-range tracking technique for process-variation-robust clock and data recovery applications


Author(s):  Jun-sheng Lv, You Li, Yu-mei Zhou, Jian-zhong Zhao, Hai-hua Shen, Feng Zhang

Affiliation(s):  Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; more

Corresponding email(s):   lvjunsheng@ime.ac.cn, shenhh@ucas.ac.cn, zhangfeng_ime@ime.ac.cn

Key Words:  Clock and data recovery, Digital loop filter, Phase interpolator


Jun-sheng Lv, You Li, Yu-mei Zhou, Jian-zhong Zhao, Hai-hua Shen, Feng Zhang. Wide-range tracking technique for process-variation-robust clock and data recovery applications[J]. Frontiers of Information Technology & Electronic Engineering, 2017, 18(12): 729-737.

@article{title="Wide-range tracking technique for process-variation-robust clock and data recovery applications",
author="Jun-sheng Lv, You Li, Yu-mei Zhou, Jian-zhong Zhao, Hai-hua Shen, Feng Zhang",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="18",
number="5",
pages="729-737",
year="2017",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1500410"
}

%0 Journal Article
%T Wide-range tracking technique for process-variation-robust clock and data recovery applications
%A Jun-sheng Lv
%A You Li
%A Yu-mei Zhou
%A Jian-zhong Zhao
%A Hai-hua Shen
%A Feng Zhang
%J Frontiers of Information Technology & Electronic Engineering
%V 18
%N 5
%P 729-737
%@ 1869-1951
%D 2017
%I Zhejiang University Press & Springer

TY - JOUR
T1 - Wide-range tracking technique for process-variation-robust clock and data recovery applications
A1 - Jun-sheng Lv
A1 - You Li
A1 - Yu-mei Zhou
A1 - Jian-zhong Zhao
A1 - Hai-hua Shen
A1 - Feng Zhang
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 18
IS - 5
SP - 729
EP - 737
%@ 1869-1951
Y1 - 2017
PB - Zhejiang University Press & Springer
ER -


Abstract: 
A wide-range tracking technique for clock and data recovery (CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because of the use of digital circuits in the design, CDR is not sensitive to process and power supply variations. To verify the technique, the whole CDR circuit is implemented using 65-nm CMOS technology. Measurements show that the tracking range of CDR is greater than ±6×10−3 at 5 Gb/s. The receiver has good jitter tolerance performance and achieves a bit error rate of <10–12. The re-timed and re-multiplexed serial data has a root-mean-square jitter of 6.7 ps.

The manuscript proposed a wide range tracking technique for clock data recovery (CDR) circuit. Due to digital CDR controller with calibration, the tracking range was extended. Moreover, the testing results have verified the design technology. This paper is well structured and the presentation is clear.

一种针对工艺变化鲁棒性时钟数据恢复应用的宽范围追踪技术

概要:本文提出了一种针对时钟数据恢复电路的宽范围追踪技术。与传统技术相比,本文采用带校准的数字时钟数据恢复控制器,拓展了追踪范围;同时,时钟数据恢复电路对工艺和电源电压的变化不再敏感。为了验证该技术,整个时钟数据恢复电路采用65 nm CMOS工艺实现。测试结果表明在5 Gb/s数据率下,追踪范围大于±6×10−3。整体接收器拥有良好的抖动容限,且误码率达到了<10−2。重新采样和串化后的串行数据的均方根抖动仅为6.7 ps。

关键词:时钟数据恢复;数字滤波器;相位插值器

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

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