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Received: 2003-03-18

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Journal of Zhejiang University SCIENCE A 2004 Vol.5 No.9 P.1102~1105

http://doi.org/10.1631/jzus.2004.1102


A front-end automation tool supporting design, verification and reuse of SOC


Author(s):  YAN Xiao-lang, YU Long-li, WANG Jie-bing

Affiliation(s):  Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China; more

Corresponding email(s):   longli_yu@saianmicro.com, jiebing_wang@saianmicro.com

Key Words:  System-On-Chip, Verilog, HDL, Verification, Reuse


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YAN Xiao-lang, YU Long-li, WANG Jie-bing. A front-end automation tool supporting design, verification and reuse of SOC[J]. Journal of Zhejiang University Science A, 2004, 5(9): 1102~1105.

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Abstract: 
This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

[1] Bening, L., Hornung, B., Pflederer, R., 2001. Hardware Description Language-Embedded Regular Expression Support for Module Iteration and Interconnection. Proc. International Hardware Description Language Conference.

[2] Bening, L., Foster, H., 2001. Principles of Verifiable RTL Design, Second Edition. Kluwer Academics, USA, p. 31-37.

[3] Cummings, C.E., 2001. Verilog-2001 Behavioral and Synthesis Enhancements. HDLCON2001, Rev1.3.

[4] Davis, B., Mudge, T., 1995. A Verilog Preprocessor for Representing Datapath Components. Proceedings of the 4th International Verilog Conference, p.90-98.

[5] IEEE Std 1364, 1995. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language.

[6] IEEE Std 1364, 2001. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language.

[7] Keating, M., Bricaud, P., 2002. Reuse Methodology Manual, 3rd edition. Kluwer Academics.

Open peer comments: Debate/Discuss/Question/Opinion

<1>

Pratik<protik.seeker@gmail.com>

2010-10-15 04:17:23

yea even I can't download. Would be nice if u can check the link

Thanks

hans ziegler<hazi@eircom.net>

2010-07-29 06:31:26

Thanks

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