CLC number: TN402
On-line Access:
Received: 2003-03-18
Revision Accepted: 2003-06-12
Crosschecked: 0000-00-00
Cited: 1
Clicked: 9998
YAN Xiao-lang, YU Long-li, WANG Jie-bing. A front-end automation tool supporting design, verification and reuse of SOC[J]. Journal of Zhejiang University Science A, 2004, 5(9): 1102-1105.
@article{title="A front-end automation tool supporting design, verification and reuse of SOC",
author="YAN Xiao-lang, YU Long-li, WANG Jie-bing",
journal="Journal of Zhejiang University Science A",
volume="5",
number="9",
pages="1102-1105",
year="2004",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.2004.1102"
}
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%A WANG Jie-bing
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%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.2004.1102
TY - JOUR
T1 - A front-end automation tool supporting design, verification and reuse of SOC
A1 - YAN Xiao-lang
A1 - YU Long-li
A1 - WANG Jie-bing
J0 - Journal of Zhejiang University Science A
VL - 5
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%@ 1869-1951
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DOI - 10.1631/jzus.2004.1102
Abstract: This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.
[1] Bening, L., Hornung, B., Pflederer, R., 2001. Hardware Description Language-Embedded Regular Expression Support for Module Iteration and Interconnection. Proc. International Hardware Description Language Conference.
[2] Bening, L., Foster, H., 2001. Principles of Verifiable RTL Design, Second Edition. Kluwer Academics, USA, p. 31-37.
[3] Cummings, C.E., 2001. Verilog-2001 Behavioral and Synthesis Enhancements. HDLCON2001, Rev1.3.
[4] Davis, B., Mudge, T., 1995. A Verilog Preprocessor for Representing Datapath Components. Proceedings of the 4th International Verilog Conference, p.90-98.
[5] IEEE Std 1364, 1995. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language.
[6] IEEE Std 1364, 2001. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language.
[7] Keating, M., Bricaud, P., 2002. Reuse Methodology Manual, 3rd edition. Kluwer Academics.
Open peer comments: Debate/Discuss/Question/Opinion
<1>
Pratik<protik.seeker@gmail.com>
2010-10-15 04:17:23
yea even I can't download. Would be nice if u can check the link
Thanks
hans ziegler<hazi@eircom.net>
2010-07-29 06:31:26
Thanks