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Journal of Zhejiang University SCIENCE A 2009 Vol.10 No.2 P.172~178


Design of adiabatic two’s complement multiplier-accumulator based on CTGAL

Author(s):  Peng-jun WANG, Jian XU, Shi-yan YING

Affiliation(s):  Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China; more

Corresponding email(s):   wangpengjun@nbu.edu.cn

Key Words:  CTGAL circuit, Adiabatic circuit, Booth arithmetic, Multiplier, Two&rsquo, s complement MAC

Peng-jun WANG, Jian XU, Shi-yan YING. Design of adiabatic two’s complement multiplier-accumulator based on CTGAL[J]. Journal of Zhejiang University Science A, 2009, 10(2): 172~178.

@article{title="Design of adiabatic two’s complement multiplier-accumulator based on CTGAL",
author="Peng-jun WANG, Jian XU, Shi-yan YING",
journal="Journal of Zhejiang University Science A",
publisher="Zhejiang University Press & Springer",

%0 Journal Article
%T Design of adiabatic two’s complement multiplier-accumulator based on CTGAL
%A Peng-jun WANG
%A Jian XU
%A Shi-yan YING
%J Journal of Zhejiang University SCIENCE A
%V 10
%N 2
%P 172~178
%@ 1673-565X
%D 2009
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.A0820013

T1 - Design of adiabatic two’s complement multiplier-accumulator based on CTGAL
A1 - Peng-jun WANG
A1 - Jian XU
A1 - Shi-yan YING
J0 - Journal of Zhejiang University Science A
VL - 10
IS - 2
SP - 172
EP - 178
%@ 1673-565X
Y1 - 2009
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.A0820013

We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic (CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two&rsquo;s complement multiplier-accumulator (MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor (CMOS) logic.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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