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Journal of Zhejiang University SCIENCE A 2009 Vol.10 No.2 P.172~178

http://doi.org/10.1631/jzus.A0820013


Design of adiabatic two’s complement multiplier-accumulator based on CTGAL


Author(s):  Peng-jun WANG, Jian XU, Shi-yan YING

Affiliation(s):  Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China; more

Corresponding email(s):   wangpengjun@nbu.edu.cn

Key Words:  CTGAL circuit, Adiabatic circuit, Booth arithmetic, Multiplier, Two&rsquo, s complement MAC


Peng-jun WANG, Jian XU, Shi-yan YING. Design of adiabatic two’s complement multiplier-accumulator based on CTGAL[J]. Journal of Zhejiang University Science A, 2009, 10(2): 172~178.

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author="Peng-jun WANG, Jian XU, Shi-yan YING",
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%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.A0820013

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T1 - Design of adiabatic two’s complement multiplier-accumulator based on CTGAL
A1 - Peng-jun WANG
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A1 - Shi-yan YING
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.A0820013


Abstract: 
We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic (CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two&rsquo;s complement multiplier-accumulator (MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor (CMOS) logic.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

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