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Journal of Zhejiang University SCIENCE A 2009 Vol.10 No.2 P.301~310

http://doi.org/10.1631/jzus.A0820024


High-performance hardware architecture of elliptic curve cryptography processor over GF(2163)


Author(s):  Yong-ping DAN, Xue-cheng ZOU, Zheng-lin LIU, Yu HAN, Li-hua YI

Affiliation(s):  Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, China

Corresponding email(s):   dyphhl@gmail.com

Key Words:  Elliptic curve cryptography (ECC), Scalar multiplication, Hardware implementation


Yong-ping DAN, Xue-cheng ZOU, Zheng-lin LIU, Yu HAN, Li-hua YI. High-performance hardware architecture of elliptic curve cryptography processor over GF(2163)[J]. Journal of Zhejiang University Science A, 2009, 10(2): 301~310.

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author="Yong-ping DAN, Xue-cheng ZOU, Zheng-lin LIU, Yu HAN, Li-hua YI",
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doi="10.1631/jzus.A0820024"
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%T High-performance hardware architecture of elliptic curve cryptography processor over GF(2163)
%A Yong-ping DAN
%A Xue-cheng ZOU
%A Zheng-lin LIU
%A Yu HAN
%A Li-hua YI
%J Journal of Zhejiang University SCIENCE A
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%P 301~310
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%D 2009
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.A0820024

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T1 - High-performance hardware architecture of elliptic curve cryptography processor over GF(2163)
A1 - Yong-ping DAN
A1 - Xue-cheng ZOU
A1 - Zheng-lin LIU
A1 - Yu HAN
A1 - Li-hua YI
J0 - Journal of Zhejiang University Science A
VL - 10
IS - 2
SP - 301
EP - 310
%@ 1673-565X
Y1 - 2009
PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.A0820024


Abstract: 
We propose a novel high-performance hardware architecture of processor for elliptic curve scalar multiplication based on the Lopez-Dahab algorithm over GF(2163) in polynomial basis representation. The processor can do all the operations using an efficient modular arithmetic logic unit, which includes an addition unit, a square and a carefully designed multiplication unit. In the proposed architecture, multiplication, addition, and square can be performed in parallel by the decomposition of computation. The point addition and point doubling iteration operations can be performed in six multiplications by optimization and solution of data dependency. The implementation results based on Xilinx VirtexII XC2V6000 FPGA show that the proposed design can do random elliptic curve scalar multiplication GF(2163) in 34.11 μs, occupying 2821 registers and 13 376 LUTs.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

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[3] Balasubramaniam, P., Karthikeyan, E., 2007. Elliptic curve scalar multiplication algorithm using complementary recoding. Appl. Math. Comput., 190(1):51-56.

[4] Cheung, R.C.C., Telle, N.J., Luk, W., Cheung, P.Y.K., 2005. Customizable elliptic curve cryptosystems. IEEE Tran. Very Large Scale Integr. Syst., 13(9):1048-1059.

[5] Itoh, T., Tsujii, S., 1988. A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases. Inf. Comput., 78(3):171-177.

[6] Lopez, J., Dahab, R., 1999. Fast multiplication on elliptic curves over GF(2m) without precomputation. LNCS, 1717:316-327.

[7] Meurice de Dormale, G., Quisquater, J.J., 2007. High-speed hardware implementations of elliptic curve cryptography: a survey. J. Syst. Archit., 53(2-3):72-84.

[8] Rodríguez-Henríquez, F., Saqib, N.A., Díaz-Pérez, A., 2004. A fast parallel implementation of elliptic curve point multiplication over GF(2m). Microprocess. Microsyst., 28(5-6):329-339.

[9] Sakiyama, K., Batina, L., Preneel, B., Verbauwhede, I., 2006. Superscalar Coprocessor for High-speed Curve-based Cryptography. Proc. 8th Int. Workshop Cryptographic Hardware and Embedded Systems, 4249:415-429.

[10] Sakiyama, K., Batina, L., Preneel, B., Verbauwhede, I., 2007. Multicore curve-based cryptoprocessor with reconfigurable modular arithmetic logic units over GF(2m). IEEE Trans. Comput., 56(9):1269-1282.

[11] Shu, C., Gaj, K., El-Ghazawi, T., 2005. Low Latency Elliptic Curve Cryptography Accelerators for NIST Curves on Binary Fields. Proc. IEEE Int. Conf. on Field-programmable Technology, p.309-310.

[12] Sozzani, F., Bertoni, G., Turcato, S., Breveglieri, L., 2005. A Parallelized Design for an Elliptic Curve Cryptosystem Coprocessor. Proc. Int. Conf. on Information Technology: Coding and Computing, p.626-630.

[13] Wu, H., 2002. Bit-parallel finite field multiplier and squarer using polynomial basis. IEEE Trans. Comput., 51(7):750-758.

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