JZUS - Journal of Zhejiang University SCIENCE

Frontiers of Information Technology & Electronic Engineering 2016 Vol.17 No.10 P.1056-1066

Design and analysis of carbon nanotube FET based quaternary full adders

Author(s): Mohammad Hossein Moaiyeri, Shima Sedighiani, Fazel Sharifi, Keivan Navi
Affiliation(s): Faculty of Electrical Engineering, Shahid Beheshti University, Tehran 1983963113, Iran; more
Corresponding email(s): h_moaiyeri@sbu.ac.ir
Key Words: Nanoelectronics, Carbon nanotube FET, Multiple-valued logic, Quaternary logic

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Abstract: CMOS binary logic is limited by short channel effects, power density, and interconnection restrictions. The effective solution is non-silicon multiple-valued logic (MVL) computing. This study presents two high-performance quaternary full adder cells based on carbon nanotube field effect transistors (CNTFETs). The proposed designs use the unique properties of CNTFETs such as achieving a desired threshold voltage by adjusting the carbon nanotube diameters and having the same mobility as p-type and n-type devices. The proposed circuits were simulated under various test conditions using the Synopsys HSPICE simulator with the 32 nm Stanford comprehensive CNTFET model. The proposed designs have on average 32% lower delay, 68% average power, 83% energy consumption, and 77% static power compared to current state-of-the-art quaternary full adders. Simulation results indicated that the proposed designs are robust against process, voltage, and temperature variations, and are noise tolerant.

In this paper two CNTFET based quaternary full adder cells design is proposed. The proposed design uses the unique properties of CNTFETs such as having desired threshold voltage by adjusting the CNT diameters and having same mobility of p-type and n-type devices. The proposed circuits are simulated under various test conditions using Synopsys HSPICE simulator with 32 nm Stanford comprehensive CNTFET model.

碳纳米管场效应管四进制全加器设计与分析

概要：CMOS二进制逻辑受短沟道效应、功率密度及互连约束等条件的限制。非硅多值逻辑计算是克服上述问题的一种有效方案。本研究在碳纳米管场效应管（carbon nanotube field effect transistors, CNTFET）的基础上提出了两种高性能四进制全加单元。该全加单元利用了CNTFET独有的特性，如目标电压阈值可通过调整碳纳米管管径控制、CNTFET具有与p型和n型器件相同的迁移性。通过在Synopsys HSPICE中使用32 nm斯坦福综合CNTFET模型，在多种测试条件下对所述电路单元进行了仿真。与当前水平的四进制全加器相比，本文所采用的设计平均降低延迟32%，所需平均功率、能耗及静态功率分别为现有水平的68%、83%及77%。仿真结果表明，所述设计在生产制程、电压、温度变化、噪声耐受方面具有较好的鲁棒性。

关键词：纳米电子；碳纳米管场效应管；多值逻辑；四进制逻辑

Reference

[1]Asif, S., Vesterbacka, M., 2012. Performance analysis of radix-4 adders. Integr. VLSI J., 45(2):111-120.

[2]Balamurugan, G., Shanbhag, N.R., 2001. The twin-transistor noise-tolerant dynamic circuit technique. IEEE J. Sol.-State Circ., 36(2):273-280.

[3]Chen, Y., Wang, B., Poa, P.C.H., et al., 2007. (n, m) selectivity of single-walled carbon nanotubes by different carbon precursors on Co-Mo catalysts. J. Am. Chem. Soc., 129(29):9014-9019.

[4]da Silva, R.C.G., Boudinov, H.I., Carro, L., 2006. A low power high performance CMOS voltage-mode quaternary full adder. IFIP Int. Conf. on Very Large Scale Integration, p.1130-1133.

[5]Datla, R., 2009. Design and Validation of Quaternary Arithmetic Circuits. PhD Thesis, Southern Methodist University, USA.

[6]Datla, S.R., Thornton, M.A., Hendrix, L., et al., 2009. Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with System Verilog©. 39th IEEE Int. Symp. on Multiple-Valued Logic, p.256-261.

[7]Deng, J., 2007. Device Modeling and Circuit Performance Evaluation for Nanoscale Devices: Silicon Technology Beyond 45 nm Node and Carbon Nanotube Field Effect Transistors. PhD Thesis, Stanford University, USA.

[8]Deng, J., Wong, H.S.P., 2007a. A compact SPICE model for carbon-nanotube field-effect transistors including non-idealities and its application—Part I: model of the intrinsic channel region. IEEE Trans. Electron Dev., 54(12): 3186-3194.

[9]Deng, J., Wong, H.S.P., 2007b. A compact SPICE model for carbon-nanotube field-effect transistors including non-idealities and its application—Part II: full device model and circuit performance benchmarking. IEEE Trans. Electron Dev., 54(12):3195-3205.

[10]Dubrova, E., 1999. Multiple-valued logic in VLSI: challenges and opportunities. Proc. NORCHIP Conf., p.340-350.

[11]Gelao, G., Marani, R., Diana, R., et al., 2011. Semi-empirical SPICE model for n-type conventional CNTFETs. IEEE Trans. Nanotechnol., 10(3):506-512.

[12]Hurst, S.L., 1984. Multiple-valued logic—its status and its future. IEEE Trans. Comput., 33(12):1160-1179.

[13]Kim, Y.B., Kim, Y.B., Lombardi, F., 2009. Novel design methodology to optimize the speed and power of the CNTFET circuits. 52nd IEEE Int. Midwest Symp. on Circuits and Systems, p.1130-1133.

[14]Liang, J., Chen, L., Han, J., et al., 2014. Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs. IEEE Trans. Nanotechnol., 13(4): 695-708.

[15]Lin, A., Patil, N., Ryu, K., et al., 2009. Threshold voltage and on–off ratio tuning for multiple-tube carbon nanotube FETs. IEEE Trans. Nanotechnol., 8(1):4-9.

[16]Lin, S., Kim, Y.B., Lombardi, F., 2011. CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol., 10(2):217-225.

[17]Mansoori, G.A., Soelaiman, T.F., 2005. Nanotechnology—an introduction for the standards. J. ASTM Int., 2(6):1-21.

[18]Marani, R., Perri, A.G., 2011. A compact, semi-empirical model of carbon nanotube field effect transistors oriented to simulation software. Current Nanosci., 7(2):245-253.

[19]Marani, R., Perri, A.G., 2012. A DC model of carbon nanotube field effect transistor for CAD applications. Int. J. Electron., 99(3):427-444.

[20]Marani, R., Perri, A.G., 2014. Modelling of CNTFETs for computer aided design of A/D electronic circuits. Current Nanosci., 10(3):326-333.

[21]Marani, R., Gelao, G., Perri, A.G., 2013. Modelling of carbon nanotube field effect transistors oriented to SPICE software for A/D circuit design. Microelectron. J., 44(1):33-39.

[22]Marani, R., Gelao, G., Perri, A.G., 2014. Comparison of ABM SPICE library with Verilog-A for compact CNTFET model implementation. Current Nanosci., 8(4):556-565.

[23]Moaiyeri, M.H., Doostaregan, A., Navi, K., 2011. Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circ. Dev. Syst., 5(4):285-296.

[24]Moaiyeri, M.H., Navi, K., Hashemipour, O., 2012. Design and evaluation of CNFET-based quaternary circuits. Circ. Syst. Signal Process., 31(5):1631-1652.

[25]Navi, K., Doostaregan, A., Moaiyeri, M.H., et al., 2011. A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders. Fuzzy Sets Syst., 185(1):111-124.

[26]Patel, V., Gurumurthy, K.S., 2010. Arithmetic operations in multi-valued logic. Int. J. VLSI Des. Commun. Syst., 1(1):21-32.

[27]Pedram, M., Wu, X., 1997. A new description of MOS circuits at switch-level with applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 80(10):1892-1901.

[28]Raychowdhury, A., Roy, K., 2005. Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol., 4(2):168-179.

[29]Raychowdhury, A., Roy, K., 2007. Carbon nanotube electronics: design of high-performance and low-power digital circuits. IEEE Trans. Circ. Systems I, 54(11):2391-2401.

[30]Sharifi, F., Moaiyeri, M.H., Navi, K., et al., 2015. Quaternary full adder cells based on carbon nanotube FETs. J. Comput. Electron., 14(3):762-772.

[31]Thoidis, I., Soudris, D., Karafyllidis, I., et al., 1998. Quaternary voltage-mode CMOS circuits for multiple-valued logic. IEE Proc.-Circ. Dev. Syst., 145(2):71-77.

[32]Wu, X., 1992. Theory of transmission switches and its application to design of CMOS digital circuits. Int. J. Circ. Theory Appl., 20(4):349-356.

[33]Wu, X., Prosser, F., 1996. Design theory of digital circuits at switch level. Sci. China Technol. Sci., 39(4):424-434.

[34]Yang, F., Wang, X., Zhang, D., et al., 2014. Chirality-specific growth of single-walled carbon nanotubes on solid alloy catalysts. Nature, 510(7506):522-524.

Open peer comments: Debate/Discuss/Question/Opinion

<1>

Anna Gina Perri@Department of Electrical and Information Engineering, Polytechnic University of Bari, ITALY<annagina.perri@poliba.it>

2016-12-12 18:49:50

Two new CNTFET based quaternary full adder cells are proposed. According to properties of CNTFETs, the design of MVL circuits is easier and efficient compared to using MOSFETs.
The circuits are examined using a HSPICE simulator with a 32 nm CNTFET model.
The simulation results, conducted under various conditions, indicate that the proposed circuits are faster, consume less power, and consequently have a lower energy consumption than the state-of-the-art quaternary full adders.
The paper is well-written and well-organized and clearly delivers the message to the reader. In particular:
1. There are no technical errors and/or inconsistencies.
2. The Statements are clear, as well as the Conclusions.
3. The level of English is good, Figures are adequate and References are current.
According to my opinion, this paper does not need any review and it may be published.
My only suggestion is to add in References the following two papers:

R. Marani, A.G. Perri: “A Comparison of CNTFET Models through the Design of a SRAM Cell”, ECS Journal of Solid State Science and Technology, vol. 5(10), 2016, pp. M118-M126, doi:10.1149/2.0161610jss.

R. Marani, A.G. Perri: “A Simulation Study of Analogue and Logic Circuits with CNTFETs”, ECS Journal of Solid State Science and Technology, vol. 5(6), 2016, pp. M38-M43, doi:10.1149/2.0121605jss.

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碳纳米管场效应管四进制全加器设计与分析

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