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CLC number: TP312

On-line Access: 2016-02-02

Received: 2015-05-25

Revision Accepted: 2015-08-24

Crosschecked: 2015-11-24

Cited: 2

Clicked: 1820

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Xin Li

http://orcid.org/0000-0002-4859-2477

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Frontiers of Information Technology & Electronic Engineering  2016 Vol.17 No.2 P.160-172

http://doi.org/10.1631/FITEE.1500168


An efficient bi-objective optimization framework for statistical chip-level yield analysis under parameter variations


Author(s):  Xin Li, Jin Sun, Fu Xiao, Jiang-shan Tian

Affiliation(s):  1Technology Innovation Center, Jiangsu Academy of Safety Science and Technology, Nanjing 210042, China; more

Corresponding email(s):   lin65002@hotmail.com

Key Words:  Parameter variations, Parametric yield, Multi-objective optimization, Chebyshev affine, Adaptive weighted sum


Xin Li, Jin Sun, Fu Xiao, Jiang-shan Tian. An efficient bi-objective optimization framework for statistical chip-level yield analysis under parameter variations[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(2): 160-172.

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Abstract: 
With shrinking technology, the increase in variability of process, voltage, and temperature (PVT) parameters significantly impacts the yield analysis and optimization for chip designs. Previous yield estimation algorithms have been limited to predicting either timing or power yield. However, neglecting the correlation between power and delay will result in significant yield loss. Most of these approaches also suffer from high computational complexity and long runtime. We suggest a novel bi-objective optimization framework based on chebyshev affine arithmetic (CAA) and the adaptive weighted sum (AWS) method. Both power and timing yield are set as objective functions in this framework. The two objectives are optimized simultaneously to maintain the correlation between them. The proposed method first predicts the guaranteed probability bounds for leakage and delay distributions under the assumption of arbitrary correlations. Then a power-delay bi-objective optimization model is formulated by computation of cumulative distribution function (CDF) bounds. Finally, the AWS method is applied for power-delay optimization to generate a well-distributed set of Pareto-optimal solutions. Experimental results on ISCAS benchmark circuits show that the proposed bi-objective framework is capable of providing sufficient trade-off information between power and timing yield.

The article looks fine.

一种基于参数扰动的芯片成品率双目标优化框架

目的:基于工艺参数扰动及环境参数扰动,实现对芯片漏电功耗成品率及芯片时延成品率的双目标优化,得到分布均匀的帕累托优化解集。
创新点:考虑分布不确定的工艺参数扰动及环境参数扰动,在任意相关性下利用CAA理论对漏电功耗成品率及芯片时延成品率进行有效估算,降低计算复杂度,并根据AWS方法对漏电功耗成品率及芯片时延成品率同时进行优化,取得了分布均匀的优化解,便于设计人员灵活选择优化解。
方法:首先,考虑工艺参数及环境参数的扰动不确定性,提出一种能够处理任意相关性的漏电功耗及芯片时延概率分布边界估算方法。然后,通过计算累积分布边界构造功耗-时延成品率双目标优化模型。最后,利用AWS方法同时优化漏电功耗成品率及芯片时延成品率,得到一组分布均匀的帕累托优化解,进而提供漏电功耗成品率与芯片时延成品率间的均衡优化信息。
结论:针对工艺参数及环境参数的扰动不确定性,提出了一种能够处理任意相关性的芯片成品率双目标优化算法,得到了一组分布均匀的帕累托优化解。

关键词:参数扰动;参数成品率;多目标优化;切比雪夫仿射;自适应加权求和

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