Full Text:   <2066>

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CLC number: TP389.1

On-line Access: 2023-05-31

Received: 2022-10-14

Revision Accepted: 2023-05-31

Crosschecked: 2023-03-02

Cited: 0

Clicked: 900

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Qiankun WANG

https://orcid.org/0000-0002-3723-3444

Guangyu SUN

https://orcid.org/0000-0002-7315-6589

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Frontiers of Information Technology & Electronic Engineering  2023 Vol.24 No.5 P.731-741

http://doi.org/10.1631/FITEE.2200463


COPPER: a combinatorial optimization problem solver with processing-in-memory architecture


Author(s):  Qiankun WANG, Xingchen LI, Bingzhe WU, Ke YANG, Wei HU, Guangyu SUN, Yuchao YANG

Affiliation(s):  School of Software & Microelectronics, Peking University, Beijing 100871, China; more

Corresponding email(s):   gsun@pku.edu.cn

Key Words:  Combinatorial optimization, Chaotic simulated annealing, Processing-in-memory


Qiankun WANG, Xingchen LI, Bingzhe WU, Ke YANG, Wei HU, Guangyu SUN, Yuchao YANG. COPPER: a combinatorial optimization problem solver with processing-in-memory architecture[J]. Frontiers of Information Technology & Electronic Engineering, 2023, 24(5): 731-741.

@article{title="COPPER: a combinatorial optimization problem solver with processing-in-memory architecture",
author="Qiankun WANG, Xingchen LI, Bingzhe WU, Ke YANG, Wei HU, Guangyu SUN, Yuchao YANG",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="24",
number="5",
pages="731-741",
year="2023",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2200463"
}

%0 Journal Article
%T COPPER: a combinatorial optimization problem solver with processing-in-memory architecture
%A Qiankun WANG
%A Xingchen LI
%A Bingzhe WU
%A Ke YANG
%A Wei HU
%A Guangyu SUN
%A Yuchao YANG
%J Frontiers of Information Technology & Electronic Engineering
%V 24
%N 5
%P 731-741
%@ 2095-9184
%D 2023
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2200463

TY - JOUR
T1 - COPPER: a combinatorial optimization problem solver with processing-in-memory architecture
A1 - Qiankun WANG
A1 - Xingchen LI
A1 - Bingzhe WU
A1 - Ke YANG
A1 - Wei HU
A1 - Guangyu SUN
A1 - Yuchao YANG
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 24
IS - 5
SP - 731
EP - 741
%@ 2095-9184
Y1 - 2023
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2200463


Abstract: 
The combinatorial optimization problem (COP), which aims to find the optimal solution in discrete space, is fundamental in various fields. Unfortunately, many COPs are NP-complete, and require much more time to solve as the problem scale increases. Troubled by this, researchers may prefer fast methods even if they are not exact, so approximation algorithms, heuristic algorithms, and machine learning have been proposed. Some works proposed chaotic simulated annealing (CSA) based on the Hopfield neural network and did a good job. However, CSA is not something that current general-purpose processors can handle easily, and there is no special hardware for it. To efficiently perform CSA, we propose a software and hardware co-design. In software, we quantize the weight and output using appropriate bit widths, and then modify the calculations that are not suitable for hardware implementation. In hardware, we design a specialized processing-in-memory hardware architecture named COPPER based on the memristor. COPPER is capable of efficiently running the modified quantized CSA algorithm and supporting the pipeline further acceleration. The results show that COPPER can perform CSA remarkably well in both speed and energy.

COPPER:具有存内计算架构的组合优化问题求解器

汪乾坤1,李星辰2,3,吴秉哲4,杨可3,胡炜5,孙广宇3,6,7,杨玉超3
1北京大学软件与微电子学院,中国北京市,100871
2北京大学计算机学院,中国北京市,100871
3北京大学集成电路学院,中国北京市,100871
4腾讯人工智能实验室,中国深圳市,518057
5福州大学物理与信息工程学院,中国福州市,350116
6北京集成电路高精尖创新中心,中国北京市,100871
7北京智源人工智能研究院,中国北京市,100080
摘要:组合优化问题(combinatorial optimization problem,COP)是一类在离散空间中寻找最优解的数学问题,具有广泛的应用。然而,许多组合优化问题是NP完全的,随着问题规模的增加,解决问题所需的时间急剧增加,这促使研究人员寻求更快速的解决方法,即使解不一定是最优的,如近似算法、启发式算法和机器学习算法等。一些先前的工作基于 Hopfield神经网络提出了混沌模拟退火(chaotic simulated annealing,CSA),并取得了良好的表现。然而,CSA的计算模式对当前的通用处理器并不友好,且没有专用的计算硬件。为了高效地执行CSA,我们提出一种软硬件联合的设计方案。在软件方面,我们使用适当的位宽对权重和输出进行量化,并修改那些不适合硬件实现的计算模式。在硬件方面,我们设计了一种基于忆阻器的专用存内计算硬件架构COPPER。COPPER能够高效地运行修改后的量化CSA算法,并支持流水线以获得进一步加速。结果表明,COPPER在执行CSA算法时,速度和能耗方面都十分出色。

关键词:组合优化问题;混沌模拟退火;存内计算

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