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Journal of Zhejiang University SCIENCE A 2007 Vol.8 No.10 P.1543~1552

http://doi.org/10.1631/jzus.2007.A1543


Test access to deeply embedded analog terminals within an A/MS SoC


Author(s):  NIARAKI Asli Rahebeh, MIRZAKUCHAKI Sattar, NAVABI Zainalabedin, RENOVELL Michel

Affiliation(s):  College of Electrical and Computer Engineering, Iran University of Science and Technology, 16846-13114 Tehran, Iran; more

Corresponding email(s):   niaraki@cad.ece.ut.ac.ir

Key Words:  Scalable design for testability (DfT), Reconfigurable architecture, Embedded A/MS testing, Modular testing, Built-in self test (BIST)


NIARAKI Asli Rahebeh, MIRZAKUCHAKI Sattar, NAVABI Zainalabedin, RENOVELL Michel. Test access to deeply embedded analog terminals within an A/MS SoC[J]. Journal of Zhejiang University Science A, 2007, 8(10): 1543~1552.

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author="NIARAKI Asli Rahebeh, MIRZAKUCHAKI Sattar, NAVABI Zainalabedin, RENOVELL Michel",
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doi="10.1631/jzus.2007.A1543"
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Abstract: 
This paper presents a standard scalable and reconfigurable design for testability (SR DfT) in order to increase accessibility to deeply embedded A/MS cores and to limit application of costly off-chip mixed-signal testers. SR DfT is an oscillation-based wrapper compatible with digital embedded core-based SoC test methodologies. The impact of the optimized oscillation-based wrapper design on MS SoC testing is evaluated in two directions: area and test time. Experimental results are presented for several SoCs from the ITC’02 test benchmarks with inclusion of eight analog filters.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

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