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Journal of Zhejiang University SCIENCE C 2012 Vol.13 No.9 P.702-710

http://doi.org/10.1631/jzus.C1200079


A new via chain design method considering confidence level and estimation precision


Author(s):  Xiao-hua Luo, Li-sheng Chen, Jiao-jiao Zhu, Xiao-lang Yan

Affiliation(s):  Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   luoxh@vlsi.zju.edu.cn, 05cls@zju.edu.cn

Key Words:  Poisson yield model, Via chain, Via failure rate, Confidence level, Estimation precision


Xiao-hua Luo, Li-sheng Chen, Jiao-jiao Zhu, Xiao-lang Yan. A new via chain design method considering confidence level and estimation precision[J]. Journal of Zhejiang University Science C, 2012, 13(9): 702-710.

@article{title="A new via chain design method considering confidence level and estimation precision",
author="Xiao-hua Luo, Li-sheng Chen, Jiao-jiao Zhu, Xiao-lang Yan",
journal="Journal of Zhejiang University Science C",
volume="13",
number="9",
pages="702-710",
year="2012",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C1200079"
}

%0 Journal Article
%T A new via chain design method considering confidence level and estimation precision
%A Xiao-hua Luo
%A Li-sheng Chen
%A Jiao-jiao Zhu
%A Xiao-lang Yan
%J Journal of Zhejiang University SCIENCE C
%V 13
%N 9
%P 702-710
%@ 1869-1951
%D 2012
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1200079

TY - JOUR
T1 - A new via chain design method considering confidence level and estimation precision
A1 - Xiao-hua Luo
A1 - Li-sheng Chen
A1 - Jiao-jiao Zhu
A1 - Xiao-lang Yan
J0 - Journal of Zhejiang University Science C
VL - 13
IS - 9
SP - 702
EP - 710
%@ 1869-1951
Y1 - 2012
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1200079


Abstract: 
For accurate prediction of via yield, via chains are usually fabricated on test chips to investigate issues about vias. To minimize the randomness of experiments and make the testing results more convincing, the confidence level and estimation precision of the via failure rate are investigated in this paper. Based on the poisson yield model, the method of determining an adequate number of total vias is obtained using the law of large numbers and the de Moivre-Laplace theorem. Moreover, for a specific confidence level and estimation precision, the method of determining a suitable via chain length is proposed. For area minimization, an optimal combination of total vias and via chain length is further determined. Monte Carlo simulation results show that the method is in good accordance with theoretical analyses. Results of via failure rates measured on test chips also reveal that via chains designed using the proposed method has a better performance. In addition, the proposed methodology can be extended to investigate statistical significance for other failure modes.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

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