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Received: 2012-10-17

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Journal of Zhejiang University SCIENCE C 2013 Vol.14 No.3 P.222-234

10.1631/jzus.C1200297


Novel serpentine structure design method considering confidence level and estimation precision


Author(s):  Li-sheng Chen, Xiao-hua Luo, Jiao-jiao Zhu, Fan-chao Jie, Xiao-lang Yan

Affiliation(s):  Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   luoxh@vlsi.zju.edu.cn

Key Words:  Poisson yield model, Serpentine test structure, Critical area, Average defect density, Confidence level, Estimation precision


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Li-sheng Chen, Xiao-hua Luo, Jiao-jiao Zhu, Fan-chao Jie, Xiao-lang Yan. Novel serpentine structure design method considering confidence level and estimation precision[J]. Journal of Zhejiang University Science C, 2013, 14(3): 222-234.

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author="Li-sheng Chen, Xiao-hua Luo, Jiao-jiao Zhu, Fan-chao Jie, Xiao-lang Yan",
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volume="14",
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pages="222-234",
year="2013",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C1200297"
}

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%A Li-sheng Chen
%A Xiao-hua Luo
%A Jiao-jiao Zhu
%A Fan-chao Jie
%A Xiao-lang Yan
%J Journal of Zhejiang University SCIENCE C
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%P 222-234
%@ 1869-1951
%D 2013
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1200297

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T1 - Novel serpentine structure design method considering confidence level and estimation precision
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A1 - Jiao-jiao Zhu
A1 - Fan-chao Jie
A1 - Xiao-lang Yan
J0 - Journal of Zhejiang University Science C
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SP - 222
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.C1200297


Abstract: 
Due to the importance of metal layers in the product yield, serpentine test structures are usually fabricated on test chips to extract parameters for yield prediction. In this paper, the confidence level and estimation precision of the average defect density on metal layers are investigated to minimize the randomness of experimental results and make the measured parameters more convincing. On the basis of the poisson yield model, the method to determine the total area of all serpentine test structures is obtained using the law of large numbers and the Lindeberg-Levy theorem. Furthermore, the method to determine an adequate area of each serpentine test structure is proposed under a specific requirement of confidence level and estimation precision. The results of Monte Carlo simulation show that the proposed method is consistent with theoretical analyses. It is also revealed by wafer experimental results that the method of designing serpentine test structure proposed in this paper has better performance.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

[1]Arumi, D., Rodriguez-Montanes, R., Figueras, J., 2008. Experimental characterization of CMOS interconnect open defects. IEEE Trans. CAD Integr. Circ. Syst., 27(1):123-136.

[2]Billingsley, P., 1961. The Lindeberg-Levy theorem for martingales. Proc. Am. Math. Soc., 12(5):788-792.

[3]Chen, F., Shinosky, M., Li, B., Aitken, J., Cohen, S., Bonilla, G., Simon, A., McLaughlin, P., Achanta, R., Baumann, F., et al., 2011. Invasion Percolation Model for Abnormal TDDB Characteristic of ULK Dielectrics with Cu Interconnect at Advanced Technology Nodes. IEEE Int. Conf. on Reliability Physics Symp., p.2F.2.1-2F.2.8.

[4]Fayolle, M., Gayet, P., Morand, Y., 2000. Multilevel Test Structures for Metal CMP Integration Application to Cu/SiO2 Damascene Interconnect. 3rd Annual Int. Interconnect Technology Conf., p.28-30.

[5]Gert, D.C., Enrique, M., 2008. Weak and strong laws of large numbers for coherent lower previsions. J. Stat. Plan. Inf., 138(8):2409-2432.

[6]Hess, C., Saadat, M., Inani, A., Yun, L., Matsuhashi, H., Squicciarini, M., Lindley, R., Akiya, N., Kaste, E.F., 2006. Yield Improvement Using a Fast Product Wafer Level Monitoring System. IEEE/SEMI Advanced Semiconductor Manufacturing Conf. and Workshop, p.417-422.

[7]Hess, C., Inani, A., Joag, A., Sa, Z., Spinelli, M., Zaragoza, M., Long, N., Kumar, B., 2010. Stackable Short Flow Characterization Vehicle Test Chip to Reduce Test Chip Designs, Mask Cost and Engineering Wafers. IEEE/ SEMI Conf. on Advanced Semiconductor Manufacturing, p.328-333.

[8]Hsu, C.L., Fang, J.Y., Yu, A., Lin, J., Huang, C., Wu, J.Y., Perng, D.C., 2009. Defect Study of Manufacturing Feasible Porous Low k Dielectrics Direct Polish for 45 nm Technology and Beyond. IEEE Int. Interconnect Technology Conf., p.140-142.

[9]Jeong, T.Y., Choi, S.M., Baek, D.C., Windu, S., Lee, M., Park, J., 2012. Effective Line Length of Test Structure and OTS Effect of Area Scaling on TDDB Characterization in Advanced Cu/ULK Process. IEEE Int. Reliability Physics Symp., p.BD.3.1-BD.3.4.

[10]Karthikeyan, M., Medina, L., Shiling, E., Kiesling, D., 2010. 32 nm Yield Learning Using Efficient Parallel-Test Structures. IEEE/SEMI Advanced Semiconductor Manufacturing Conf., p.1-6.

[11]Khare, J., Maly, W., Griep, S., Schmitt-Landsiedel, D., 1994. SRAM-Based Extraction of Defect Characteristics. Int. Conf. on Microelectronic Test Structures, p.98-107.

[12]Konno, N., 2002. Quantum random walks in one dimension. Quantum Inf. Process., 1(5):345-354.

[13]Kumar, M.V., Lukaszek, W., Plummer, J.D., 1997. A test structure advisor and a coupled, library-based test structure layout and testing environment. IEEE Trans. Semiconduct. Manuf., 10(3):370-383.

[14]Lin, C.S., Huang, J.H., Hong, S.R., Lo, C.S., Chuang, L.S., 2002. Integration HDP CVD Oxide Sputtering Effect for Metal Void Defect Solution. Semiconductor Manufacturing Technology Workshop, p.165-168.

[15]Lin, T.M.Z., Hsu, W.M., Lin, S.R., Wang, R.C.J., Chiu, C.C., Wu, K., 2006. Identification and Layout Modification of Copper/Low k Interconnect Dielectric Reliability Assessment by Using RVDB Test. 44th Annual IEEE Int. Reliability Physics Symp., p.687-688.

[16]Luo, X.H., Chen, L.S., Zhu, J.J., Yan, X.L., 2012. A new via chain design method considering confidence level and estimation precision. J. Zhejiang Univ.-Sci. C (Comput. & Electron.), 13(9):702-710.

[17]Michalka, T.L., Lukaszek, W., Meindl, J.D., 1990. A redundant metal-polyimide thin film interconnection process for wafer scale dimensions. IEEE Trans. Semic. Manuf., 3(4):158-167.

[18]Montgomery, D.C., Runger, G.C., 2002. Applied Statistics and Probability for Engineers (3rd Ed.). John Wiley & Sons, Inc., New York, p.356-359.

[19]Roesch, W.J., Hamada, D.J.M., 2004. Studying Yield and Reliability Relationships for Metal Defects. Workshop on Reliability of Compound Semiconductors, p.121-133.

[20]Sayah, H.R., Buehler, M.G., 1988. Comb/Serpentine/ Cross-Bridge Test Structure for Fabrication Process Evaluation. IEEE Int. Conf. on Microelectronic Test Structures, p.23-28.

[21]Stapper, C.H., 1973. Defect density distribution for LSI yield calculations. IEEE Trans. Electron Dev., 20(7):655-657.

[22]Stapper, C.H., 1983. Modeling of integrated circuit defect sensitivities. IBM J. Res. Devel., 27(6):549-557.

[23]Stapper, C.H., 1984. Modeling of defects in integrated circuit photolithographic patterns. IBM J. Res. Devel., 28(4):461-475.

[24]Tamaki, Y., Ito, M., Takimoto, Y., Hashino, M., Kawamoto, Y., 2011. New Test Structure for Evaluating Low-k Dielectric Interconnect Layers by Using Ring-Oscillators and Metal Comb/Serpentine Patterns. 24th IEEE Int. Conf. on Microelectronic Test Structures, p.125-129.

[25]Teh, W.H., Guo, L., Kumar, R., Kwong, D.L., 2005. 200-mm wafer-scale transfer of 0.18 μm dual-damascene Cu/SiO2 interconnection system to plastic substrates. IEEE Electron Dev. Lett., 26(11):802-804.

[26]Wahab, Y.A., Ahmad, A.F., Awang, Z., 2006. Comparison of Missing Metal Defect Formation on He In-Situ and Furnace Annealed Electroplated Copper Films. 4th Student Conf. on Research and Development, p.53-57.

[27]Wallmark, J.T., 1960. Design considerations for integrated electronic devices. Proc. IRE, 48(3):293-300.

[28]Welch, B.L., 1947. The generalization of ‘student’s’ problem when several different population variances are involved. Biometrika, 34(1-2):28-35.

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