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Received: 2002-05-03

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Journal of Zhejiang University SCIENCE A 2003 Vol.4 No.3 P.281~286

http://doi.org/10.1631/jzus.2003.0281


Noise and linearity optimization methods for a 1.9GHz low noise amplifier


Author(s):  GUO Wei, HUANG Da-quan

Affiliation(s):  Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   alohagw@isee.zju.edu.cn

Key Words:  RFIC, CMOS LNA, NF, noise, IP3, linearity


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GUO Wei, HUANG Da-quan. Noise and linearity optimization methods for a 1.9GHz low noise amplifier[J]. Journal of Zhejiang University Science A, 2003, 4(3): 281~286.

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Abstract: 
noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade-offs. The 1.9GHz Complementary Metal-Oxide-Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.

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Reference

[1]Floyd, B. A., Mehta, J., Camero, C. and Kenneth, K. O., 1999. A 900 MHz, 0.8μm CMOS Low Noise Amplifier with 1.2 dB Noise Figure. IEEE 1999 Custom Integrated Circuits Conference, San Diego, CA, p. 661-664

[2]Jin, W., Liu, W., Hai, C., Chan, Philip, C. H. and Hu, C., 2001. Noise modeling and characterization for 1.5V 1.8GHz SOI low-noise amplifier. IEEE Transaction on Electron Devices, 48(4):803-809.

[3]Lee, T. H., 1998. The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press.

[4]Park, P. and Kim, C. S., 2001. Linearity, Noise Optimization for Two Stage RF CMOS LNA. Proc. Of IEEE, 2:756-758.

[5]Shaeffer, D. K. and Lee, T. H., 1997. 1.5V, 1.5GHz CMOS low noise amplifier. Solid-State Circuits, IEEE Journal, 32: 745-759.

[6]Tinella, C., Fournier, J. M. and Haidar, J., 2001. Noise Contribution in A Fully Integrated 1V, 2.5GHz LNA in CMOS-SOI Technology. The 8th IEEE International Conference on, Electronics Circuits and Systems, 3: 1611-1614.

[7]Van der Ziel, A., 1986. Noise in Solid State Devices and Circuits. Wiley, New York.

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